本論文內容主要探討氮化鋁鎵/氮化鎵高電子遷移率場效電晶體使用不同表面披覆層對電性的影響。實驗使用三種表面披覆層包括傳統氮化鎵披覆層(GaN cap)，p型氮化鎵披覆層(p-GaN cap)和在MOCVD裡成長的氮化矽為披覆層(in-situ SiN cap)。實驗目的為利用不同的披覆層來提升元件的崩潰電壓和改善元件的動態電阻特性，並在製作蕭特基閘極元件前會先進行一系列的材料分析。 本實驗所製作的蕭特基閘極電晶體，在in-situ SiN cap元件上有低的閘極漏電流、(I_on/I_off )電流比值為1.71×108、低的次臨界斜率82 mV/dec以及有最大的元件崩潰電壓在汲極電流1 mA/mm下LGD = 20 μm約為1200 V。在動態特性方面p-GaN cap元件和in-situ SiN cap元件在汲極電壓100 V下動態電阻比值皆比GaN cap好，此兩種結構動態電阻比值分別為1.8和1.2。此外也利用脈衝量測去觀察三種表面披覆層之表面缺陷特性。 最後利用矽基板偏壓的方式去觀察元件在進行切換開關時電子被表面缺陷捕捉的情形，其中在GaN cap元件在量測上有較差的表現，電流回復到穩態時間最長，以及利用變溫量測的方式去計算缺陷的活化能。 ;In this work, we focus on AlGaN/GaN HEMT with different cap layers which may influence on electrical property. We use three types of cap layers including conventional GaN cap,p-type GaN cap and in-situ SiN grown in the MOCVD. The purpose of this study is to improve device breakdown voltage and dynamic Ron. Material analysis is discussed before fabricating Schottky device. Among the Schottky devices with different cap layers, in-situ SiN cap device has the lowest gate leakage current, high on/off current ratio 1.71×108, subthreshold slope at 82 mV/dec, and have the largest breakdown voltage about 1200V at LGD = 20 μm. In terms of dynamic Ron, p-GaN device and in-situ SiN device stressed at VDS = 100V show better results than GaN cap. The corresponding dynamic Ron ratio are 1.8 and 1.2, respectively. In addition, we use pulse measurement to investigate the surface trap in these three structure. Finally, in this experiment we use substrate bias to separate device with the contributions of surface- and buffer-induced trapping effect. Among three structure, device with GaN cap show the worst performance, the current recovery to the steady state requiring longer time. The activation energy associated with the defects are analyzed by temperature-dependent dynamic Ron measurement.
