銻砷化鎵/砷化銦鎵穿隧式場效電晶體製作與特性研究

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題名:	銻砷化鎵/砷化銦鎵穿隧式場效電晶體製作與特性研究
作者:	高楷博;Kao,Kai-Po
貢獻者:	電機工程學系
關鍵詞:	穿隧式場效電晶體;次臨限斜率;能帶至能帶穿隧;銻砷化鎵;砷化銦鎵;TFET;subthreshold swing;band-to-band tunneling;GaAaSb;InGaAs
日期:	2015-08-04
上傳時間:	2015-09-23 14:45:57 (UTC+8)
出版者:	國立中央大學
摘要:	穿隧式場效電晶體其載子是以能帶穿隧的方式來產生電流，在室溫條件下，次臨限斜率能小於60 mV/decade，有別於傳統金氧半場效電晶體其載子是以漂移-擴散的方式來產生電流，次臨限斜率會被kT/q所限制。本論文所使用的磊晶為p+-i-n+摻雜的銻砷化鎵/砷化銦鎵異質結構，源極為p+銻砷化鎵，其碳元素摻雜濃度大於5 × 1019 /cm3，砷的莫耳比例為51%，銻的莫耳比例為49%；汲極為n+砷化銦鎵，其矽元素摻雜濃度大於1 × 1018 /cm3，銦的莫耳比例為53%，鎵的莫耳比例為47%，通道i層厚度為150 nm。藉由光學曝光與濕蝕刻的方式成功製作出微米尺寸的穿隧式場效電晶體，首先進行溫度相依的電性量測，並分析出三種不同的電流產生機制，第一區為類似Shockley-Read-Hall產生與複合電流區，第二區為陷阱輔助穿隧區，第三區為直接穿隧區。把氧化鋁/氧化鉿的等效氧化層厚度由2 nm縮小到1.5 nm以提升閘極對通道的控制能力，薄膜沉積後將爐管熱退火改成快速熱退火的方法使維持良好p+-i-n+磊晶特性與介面缺陷密度，最後使用脈衝量測的方式來觀察陷阱對穿隧式場效電晶體的影響。在室溫條件下，最大導通電流由直流量測下之3.56 μA/μm提升到9.01 μA/μm，最大電流開關比由2.72 × 102提升到1.75 × 103，VDS < 0 V之負電阻的峰谷比由小於1提升到1.6，最佳次臨限斜率由298 mV/decade最佳到55 mV/decade，成功突破60 mV/decade。 ;Tunnel field effect transistors (TFETs) is based on band-to-band tunneling (BTBT) to generate the current, and subthreshold slope (S.S.) could be less than 60 mV/decade. Unlike traditional metal oxide semiconductor field effect transistors (MOSFETs), which is based on drift-diffusion carriers to generate the current, which S.S. would be limited by kT/q. For a hetero-epitaxial structure p+-i-n+ GaAsSb/InGaAs material was used in this study. Sourse is a heavy doped p+-GaAsSb, which is > 5 × 1019 /cm3 carbon doped, 51% arsenic and 49% antimony. Drain is a heavy doped n+-InGaAs, which is > 1 × 1018 /cm3 silicon doped, 51% indium and 49% gallium. The channel is a 150 nm undoped i-InGaAs layer. In this study, we use optical exposure and wet etching method to fabricate the micron size TFETs. First, investigating temperature-dependent current-voltage characteristics of TFETs, which is divided into three different transport mechanisms. First region is like Shockley–Read–Hall (SRH) generation–recombination current, second region is trap- assisted tunneling (TAT) and third region is band-to-band tunneling (BTBT). Scaling the Al2O3/HfO2 effective oxide thickness (EOT) from 2 nm to 1.5 nm improves the gate control capability to channel. Using rapid thermal annealing (RTA) method to replace the furnace post-deposition annealing (F-PDA) maintains great p+-i-n+ epitaxial behavior. Finially, using pulsed I-V measurement to reduce the impact of traps to TFETs. At room temperature, the characteristics of this device could obtain the maximum on current (Ion) from 3.56 μA/μm which is measured by directly current (DC) to 9.01 μA/μm, the highest on/off current ratio (Ion/Ioff) is from 2.72 × 102 to 1.75 × 103, the peak to valley current ratio (IP/IV) of negative differential resistance (NDR) is from < 1 to 1.6, and the minimum S.S. is from 298 mV/decade to 55 mV/decade which is beyond 60 mV/decade.
顯示於類別:	[電機工程研究所] 博碩士論文

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