晶圓圖群集特徵加速運算演算法;Improved Acceleration Algorithm for the Calculation of the Wafer Map Features

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81376

Title:	晶圓圖群集特徵加速運算演算法;Improved Acceleration Algorithm for the Calculation of the Wafer Map Features
Authors:	謝全禮;Hsieh, Chiuan-Li
Contributors:	電機工程學系
Keywords:	迴力棒特徵圖;模擬時間;加速
Date:	2019-06-26
Issue Date:	2019-09-03 15:49:16 (UTC+8)
Publisher:	國立中央大學
Abstract:	晶圓發生問題時，可分為隨機性或系統性這兩種錯誤，本文針對過去提出之迴力棒特徵圖，分析實際晶圓(WM-811K)發生問題時，是由上述何種錯誤產生所使用的演算法加以改良並進行加速。隨著科技日益進步，所用的製程更先進，晶圓的大小以及產量也為之增加，因此，在建構迴力棒特徵圖須模擬更多數量、不同尺寸的隨機晶圓圖，筆者必須改善演算法並提升運算速度，以符合新的科技趨勢。然而，建構迴力棒特徵圖的兩項重要參數—NBD(number of bad die)、NCL(number of contiguous line)之中的NCL，在先前的演算法中，根據定義用以制定演算法的過程上，制定了不當的搜尋策略，造成程式大規模耗時。隨機瑕疵種類以及晶圓尺寸同時增加，會使得時間呈非線性遞增，故本文在不違背原先定義的前提下，制定了一項新的搜尋策略，並設計新的演算法，改善模擬時間呈非線性遞增的問題。新的搜尋策略不僅提供了詳細明確的搜尋規則，在制定演算法時，更能夠從中改善原先的運算速度，得到顯著加速，亦能將該演算法以各種不同程式語言實現。 ;When a problem occurring on a wafer, it can be divided into two kinds of errors, random and systematic. In the study, we use previously proposed boomerang chart to classify the problem of real wafer (WM-811K). With the advancement of technology, the processes are more advanced, wafer size and quantity are also increased. Therefore, in the construction of boomerang chart, it is necessary to simulate a larger number and more different sizes of randomness wafer maps. We must improve the algorithm and increase the speed of the operation to meet the trend of technology. However, NCL, one of the two important parameters of boomerang chart—NBD (number of bad die) and NCL (number of contiguous line), planned by a bad strategy in previous algorithm in the process of formulating the algorithm according to the original definition. Thus, it would cause time-consuming badly. When the number of random types increase and the wafer size becomes larger, the operation time would increase nonlinearly. Therefore, the research is going to develop a new search flow without violating the original definition and designs a new algorithms to improve the problem of increasing time in simulate larger randomness wafer map. The new search strategy not only provides clear and detailed search rules, but also improves the speed of calculations larger randomness wafer map. When developing algorithms, it achieves significant acceleration. Furthermore, the algorithm can be easily implemented in various programming languages as well.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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