以90-nm CMOS 製程實現之47-GHz 壓控振盪器設計;A 47-GHz Voltage Controlled Oscillator in 90-nm CMOS Process

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/81428

請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/81428

題名:	以90-nm CMOS 製程實現之47-GHz 壓控振盪器設計;A 47-GHz Voltage Controlled Oscillator in 90-nm CMOS Process
作者:	黃才源;Huang, Tsai-Yuan
貢獻者:	電機工程學系
關鍵詞:	壓控震盪器;可變電容器;數位控制;VCO;Varactor;Digital Control
日期:	2019-07-23
上傳時間:	2019-09-03 15:53:10 (UTC+8)
出版者:	國立中央大學
摘要:	本篇論文提出一個可應用於毫米波通訊的47-GHz的壓控振盪器，採用90-nm CMOS製程實現，擁有低成本且體積小的優點。此電路使用交互耦合對的電晶體產生負電阻，使其能夠在高頻中更容易維持振盪條件，並透過緩衝器及電壓放大器輸出，使輸出功率可提高至2.7 dBm。在操作電壓1.2 V下，整體電路的功耗為49.65 mW。為了增加振盪器的可調頻寬，本文提出於振盪器電路中加入8組的可開關電容器，使振盪器可藉由切換電容達到增加調頻範圍的效果，當操作於47-GHz時的單一可調頻寬為3.16%，而總可調頻寬則可達到10.38 %。此電路在post-simulation時其在雜訊頻率1 MHz的結果為-86.82 dBc/Hz。為了提供壓控振盪器所需的8個數位控制位元，並且避免因為加入的pad數量太多而使晶片面積增加，本文提出一種低延遲、低功耗的3-Wire數位控制電路加入於壓控振盪器的電路前端，藉由SPI的通訊介面將一串數位訊號提供給3-wire電路，將訊號中的8個數位控制位元儲存於移位暫存器之後，利用並接的暫存器從接收的數位訊號中擷取出所需的8個控制位元給予壓控振盪器，此時僅需要3個輸入接腳(Clk (Clock), LE(Parallel-out Enable), D_in(Digital Data))，即可產生振盪器所需之8個數位控制位元，因此可以有效的縮減輸入數位控制位元所需的pad，而大幅減少晶片面積。 ;In this thesis, a low-cost and compact 47-GHz voltage-controlled oscillator in a 90-nm CMOS technology for millimeter-wave communication is proposed. This circuit uses the cross-coupled transistors to generate a negative resistance that makes it easier to maintain oscillation conditions at high frequencies. The VCO increase the output power to 2.7 dBm with a buffer and a voltage amplifier. The power consumption is 49.65 mW from a 1.2 V supply. In order to increase the tuning range of the oscillator, this thesis proposes to add 8 sets of switchable capacitors to the oscillator circuit, so that it can increase the tuning range of the VCO by switching the capacitors. While the oscillator is operated at 47-GHz, the single tuning range is 3.16%, and the total tuning range is 10.38%. The phase noise at 1 MHz offset from the carrier is -86.82 dBc/Hz in post-simulation. In order to provide the eight digital control bits to switch the capacitors of the VCO, and to avoid adding too much pads in this chip result in increasing the chip size, this thesis propose a low-delay and low-cost 3-wire digital control circuit that added to the VCO front end. A series of digital signals are provided to the 3-wire circuit through the communication interface of the SPI, and the digital control bits in the signal are stored in the shift register. Then, using the parallel register, the required eight control bits are extracted from the received digital signal to the VCO. At this time, only three input pins (Clk (Clock), LE(Parallel-out Enable), D_in(Digital Data)) are needed in this chip to generate the digital control bits required by the oscillator so that the pads for inputting the digital control bits can be effectively reduced, and the chip size will be greatly reduced.
顯示於類別:	[電機工程研究所] 博碩士論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
index.html		0Kb	HTML	124	檢視/開啟

在NCUIR中所有的資料項目都受到原著作權保護.

社群 sharing

資料載入中.....