| 摘要: | 本論文擬研製本地振盪訊號電路，可應用於X頻段及Ka頻段收發機中的本地振盪電路。本論文一共實現四種電路，首先使用tsmcTM 0.18 μm互補式金氧半導體製作X頻段本地振盪電路、使用tsmcTM 90 nm互補式金氧半導體製作Ka頻段本地振盪電路、與利用WINTM 0.25 μm GaN製程製作高功率及高效率本地振盪電路。
以下為本論文所實現之四種電路：
一、應用於X頻段利用疊接式耦合之四相位壓控振盪器
本電路利用疊接式耦合技術改善傳統並聯式耦合架構相位雜訊惡化之缺點，整體電路經由量測後，可調頻率為9.27 ~ 10.11 GHz (8.7%)，加入傳輸線損耗後最大輸出功率為-4.78 dBm，此時相位雜訊在1-MHz 偏移時最低為 -115.2 dBc/Hz，在供應電壓1.45 V下，功耗為9 mW，整體電路優化指標(FoM)為-185，整體晶片面積包含I/O PAD為1.096 × 0.593 mm2。
二、應用於X頻段整數型鎖相迴路
本電路包含壓控振盪器、電流模式邏輯除頻器、雙轉單緩衝放大器、真單一相位時脈除頻器、全擺幅緩衝器、相位頻率比較器、充電汞及迴路濾波器。利用上述電路合成一個鎖相迴路，並於章節中完整分析各子電路之用途及數學分析，分析雙轉單緩衝放大器需注意之問題，並提出了無死區相位頻率比較器之架構。當輸入參考頻率為37.5 MHz到39.2578125 MHz時輸出頻率能成功鎖定在9.6到10.05 GHz，除數設計為256，整體鎖相迴路功耗為39.2 mW，經由量測後參考突波大小為-45.7 dBc，鎖定後相位雜訊在1 MHz偏移時為-93.7 dBc/Hz，整體晶片面積包含I/O PAD為1.035 × 0.809 mm2。
三、應用於X頻段可調頻式回授型壓控振盪器
本電路在WINTM GaN 0.25 μm源極接地的限制下完成壓控振盪器之設計，並且在無可變電容模型的限制下，完成了可調頻機制之壓控振盪器。整體電路經由量測後，可調頻率為9.348 ~ 9.46 GHz，加入探針的損耗、傳輸線損耗和30 dB的衰減器後，最大輸出功率為27.89 dBm，此時相位雜訊在1-MHz偏移時最低為-121.62 dBc/Hz；在供應電壓19 V下，功耗為2204 mW，整體直流到射頻轉換效率為27.89%。整體晶片面積包含I/O PAD為2 × 1 mm2，電路優化指標FoMp及FoMposc分別為-195.49及-223.38。
四、應用於Ka頻段整數型鎖相迴路
本電路包含壓控振盪器、注入鎖定除頻器、電流模式邏輯除頻器、雙轉單緩衝放大器、真單一相位時脈除頻器、全擺幅緩衝器、相位頻率比較器、充電汞及迴路濾波器。利用上述電路合成一個鎖相迴路，當輸入參考頻率為103.6 MHz到108.9 MHz時輸出頻率能成功鎖定在26.52到27.88 GHz，除數設計為256，整體鎖相迴路功耗為43.9 mW，經由量測後參考突波大小為-48.9 dBc，鎖定後相位雜訊在1 MHz偏移時為-95.8 dBc/Hz，整體晶片面積包含I/O PAD為1.015 × 0.972 mm2。
;This thesis developed four local oscillator (LO) circuits for the signal source of X band and Ka band transceivers. The X-band LO was realized in tsmcTM 0.18 μm technology. The Ka-band LO was ikplemented in tsmcTM 90 nm technology. The X-band high power and high efficiency was realized in WINTM 0.25 μm GaN process. The developed LO circuits are listed as follow,
A.Implementation on X-Band Quadrature Voltage Controlled Oscillator Using Cascode Coupling Technique
The circuit improves the phase noise in traditional parallel coupling technique by using cascaded-coupling topology. After measurements, the operation frequency is from 9.27 to 10.12 GHz (i.e., 8.7% tuning range). The best phase noise is -115.2 dBc/Hz at 1-MHz offset. The output power including transmission loss is -4.78 dBm. Under 1.45-V supply voltage, the power consumption is 7.72 mW which is correspondent to an FoM of -185. The chip size includes all pads is 1.096 × 0.593 mm2.
B.Implementation on X-Band Integer-N Phase Locked Loop (PLL)
The functional circuit blocks of the designed PLL include a voltage controlled oscillator, a current mode logic divider, a differential to single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. This thesis analyzes the behavior model of PLL. Meanwhile, we also analyze the issue of the differential-to-single buffer amplifier. The thesis adopts the phase and frequency detector with zero dead zone topology. The PLL is locked from 9.6 to 10.05 GHz when reference signal is 37.5 to 39.2578125 MHz. The division ratio is 256 and the total power consumption is 39.2 mW. The reference spur is as low as -45.7 dBc and phase noise is -93.7 dBc/Hz at 1-MHz offset. The chip size includes all pads is 1.035 × 0.809 mm2.
C.Implementation on X-Band Tunable Feedback Type Voltage Controlled Oscillator
The implementation on the VCO is realized in WINTM 0.25 μm GaN process under the constraint of the via-hole at source node that makes common source topology can be only adopted. Meanwhile, no varactor model is available. After measurements, the tuning frequency is from 9.348 to 9.46 GHz, and the output power including the transmission line loss and a 30-dB attenuator is 27.89 dBm. The best phase noise is -121.62 dBc/Hz at 1-MHz offset frequency. Under the 19-V supply voltage, the total power consumption is 2204 mW. The DC-to-RF conversion efficiency is 27.89%. The FoMp and FoMposc are -195.49 and -223.38, respectively. The chip size includes all pads is 2 × 1 mm2.
D.Implementation on Ka-Band Integer-N Phase Locked Loop (PLL)
The functional blocks of PLL include a VCO, an injection locked frequency divider, a current mode logic divider, a differential-to-single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. The PLL is locked from 26.52 to 27.88 GHz when reference signal is 103.6 to 108.9 MHz. The division ratio is 256 and the total power consumption is 43.9 mW. The reference spur is -48.9 dBc and phase noise is -95.8 dBc/Hz at 1-MHz offset when PLL is locked. The chip size includes all pads is 1.015 × 0.972 mm2. |
