此論文採用tsmcTM CMOS 90 nm製程設計Ka頻段單刀雙擲切換器，以及採用WIN GaN 0.25μm製程設計X頻段之單刀雙擲切換器與單刀單擲切換器，主要研究方向以高線性度、低損耗、寬頻為設計目標。 第一顆電路為Ka頻段CMOS單刀雙擲切換器，使用的結構為串並連結構，使用兩組反向器，一組用來控制發射接收模式，另一組用來定義電位，與前一組反向器的控制電壓在閘極端形成負偏壓與零電壓。電路之插入損耗在18-44 GHz為2.05 ~ 2.93 dB，在18-44 GHz隔離度為21.1-35.2 dB，由於前級功率放大器(pre-amplifier)無法在高頻達到20 dBm之輸出，只能以IIP3反推確定IP1dB大於20 dBm，最後由於負偏壓係使用反向器建構而成，故存在約3 mW之直流功耗。 第二顆電路為X頻段GaN/SiC單刀雙擲切換器，為了解決50 四分之一波長傳輸線面積過大之問題，提出一新型單刀雙擲切換器，所用結構會在天線端往隔離端看過去產生一並聯電容電感結構，同時天線端往傳輸端看過去具有三組並聯電容電感共振結構的匹配網絡。電路插入損耗在8-12 GHz為1.2-2.6 dB，在8-12 GHz隔離度皆大於45 dB，由於前級功率放大器無法在達到大於30 dBm之輸出，只能確定IP1dB大於30 dBm。 第三顆電路為X頻段GaN/SiC單刀單擲切換器，有鑑於從第二顆晶片量測結果與模擬結果，推斷電晶體閉電容模型操作在極負偏壓下存在實際值比模型小約50%，本電路使用相對共振結構較穩定之行進波結構，目的為在滿足設計目標同時驗證推斷是否正確，從量測結果證實第二顆晶片所採用的修正是正確的。電路插入損耗在8-12 GHz為0.52-0.72 dB，在8-12 GHz隔離度皆大於4 2 dB，IP1dB由於前級功率放大器無法在高頻達大於到30 dBm之輸出，只能確定IP1dB大於30 dBm。 ;This paper adopted tsmcTM CMOS 90 nm process to design Ka-band single pole double throw (SPDT) switch. Meanwhile, the author uses the WINTM GaN/SiC 0.25 μm process to design X-band SPDT switch and single pole single throw (SPST) switch. The purposes of this research are aimed at the performances of high linearity, low loss and wide frequency. The first circuit is a Ka-band CMOS SPDT switch using a series-shunt topology. In this SPDT, a pair of inverters with complementary outputs are used to control the transmit and receive modes. Meanwhile, one of inverter is used to define the voltage level. The control voltage of the previous of inverter forms a negative bias and a zero voltage at both gate terminals. The proposed SPDT achieves an insertion loss of 2.05-2.93 dB from 18-44 GHz with isolation of 21.1-35.2 dB. Since the pre-amplifier cannot deliver power level up to 20 dBm for testing, IP1dB can only be estimated by IIP3 backward extrapolation to be greater than 20 dBm. The inverter pairs consume a DC power of 3 mW. The second circuit is a GaN/SiC X-band SPDT switch. A novel SPDT topology is proposed to overcome the large occupied area if using 50 quarter-wavelength transmission line for isolation design. The proposed topology exhibits a shunt capacitor and inductor resonator from common port to isolation port. Meanwhile, it shows a resonant matching network that includes three parallel capacitors (two Coff capacitors and one matching capacitor) and inductor structures from common port to transmission port. This particular matching network provides better isolation than that of conventional SPDT topology. The proposed SPDT achieves an insertion loss of 1.2 ~ 2.6 dB from 8-12 GHz with isolation better than 45 dB. Since the pre-power amplifier cannot achieve an output level up to 30 dBm, it can only be estimated that IP1dB is larger than 30 dBm. The third circuit is an X-band SPST switch. From the measured results of the second chip, it can be inferred that the value of off-capacitance is 50% less than device model under extremely negative bias condition. This SPST switch adopts a traveling wave topology to verify the model accuracy. The proposed SPST achieves an insertion loss of 0.52-0.72 dB from 8-12 GHz with isolation better than 42 dB. Since the pre-power amplifier cannot achieve an output up to 30 dBm, it can only be estimated that IP1dB is greater than 30 dBm.
