| 摘要: | 近年來，消費性電子產品的快速崛起帶動了資料傳輸速率的提升，為了滿足更高速的資料傳輸頻寬，高速串列傳輸技術已然成為現今主要資料傳輸技術。但隨著電子裝置的操作頻率日漸提升，電磁干擾(Electromagnetic Interference, EMI)效應越來越嚴重。在時脈產生電路中，由於集中的能量所造成的電磁干擾也將成為傳輸系統介面中的主要雜訊來源，因此，為了降低電磁干擾效應，展頻時脈技術已廣泛的應用於時脈產生器中。
此外，目前有線收發技術應用須具備向下相容的能力，這驅使設計一個具寬範圍操作之時脈產生器用以支援數種世代規格。因此，本論文參考SATA Gen1至Gen3規格，實現一個使用分數型鎖相迴路，並可適用於多世代規格之全數位展頻時脈產生器。論文中，提出具雙重相位旋轉之相位補償技巧應用於分數除頻器，針對相位補償技術應用於多規格時因為展頻之頻率範圍不同導致電磁干擾抑制能力劣化之缺陷做改良。透過相位旋轉，可有效補償瞬時時序錯誤，同時避免量化誤差的產生，實現一無擾動的真實分數除率。本論文使用TSMC 40 nm (TN40G) 1P9M CMOS製程實現，操作電壓為 0.9 V，中心操作頻率分別為6 GHz、3 GHz及1.5 GHz，並以頻率32.89 kHz之三角波作為調變訊號，向下展頻5000 ppm。展頻機制開啟後，電磁干擾抑制量分別約為22.4 dB、20.5 dB、18.8 dB。電路操作在最高頻率時的功率消耗為9.74 mW，整體晶片面積為0.9 mm2，核心電路所佔面積為0.0395 mm2。
;Recently, the rapid development of consumer electronics has led to higher transmission data rates. The high-speed serial link (HSSL) technology has become the major technique in modern data transmission to satisfy with the wider bandwidth of the transmission data. Additionally, as the operating frequency increases, the electromagnetic interference (EMI) induced by the concentrated energy of the clock generator will interfere the other equipment severely. It will be the main noise source in the transmission system. Thus, to reduce the EMI, the spread-spectrum clock generator (SSCG) has been widely employed for clock generation.
In the current wireline SerDes application, it evolves the coexistence of several specification generations. As a result, a wide range clock generator to support multi-specification generations is desirable. Therefore, this thesis presents an all-digital spread-spectrum clock generator (ADSSCG) based on a fractional-N all-digital PLL (ADPLL) for multi-specification generations which takes the SATA Gen1 to SATA Gen3 specifications as a reference material. Besides, the proposed ADSSCG presents a phase compensation technique with a dual phase-rotating approach which improved the drawback of the degraded EMI reduction due to different spread frequency ranges under multiple generation specifications with the same spread ratio. Through the phase-rotating technique, the instantaneous timing error can be effectively compensated, and it shows the ignorable quantization error. Thus, the proposed ADSSCG realized non-dithered fractional division ratios.
This work is designed in a 40 nm standard CMOS process with a supply voltage of 0.9 V. Under the operation frequency of 6 GHz, 3 GHz, and 1.5 GHz, the reduction of EMI is 22.4 dB, 20.5 dB, and 18.8 dB, respectively, with 5000 ppm down spread and 32.89 kHz triangular modulation. The power consumption is 9.74 mW at the highest operation frequency. The full chip area is 0.9 mm2 and the core area is 0.0395 mm2. |
