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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81950


    Title: 晶圓圖切割分析在增強顯著樣態識別中的應用;Application of Wafer Map Partition Analysis to Enhance the Salient Pattern Identification
    Authors: 呂東穎;Lu, Tung-Ying
    Contributors: 電機工程學系
    Keywords: 晶圓圖;錯誤樣態辨識;隨機性分析;良率分析;Wafer map;Pattern recognition;Randomness analysis;Yield analysis
    Date: 2019-11-25
    Issue Date: 2020-01-07 14:40:11 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 在本篇論文中,主要分為兩大類方法,第一種方法是利用深度學習的方式,藉由實際晶圓來訓練類神經網路的模型,用以判別晶圓的錯誤樣態。我們所使用的實際晶圓為台積電所提供的WM-811K晶圓資料庫,其中的錯誤樣態可分為以下九類,Center、Donut、Scratch、Edge-Ring、Edge-Loc、Loc、Near-Full、Random、None,因此,所訓練的類神經網路模型可用來分辨此九種錯誤樣態。
    第二種方法是建立一個判斷晶圓缺陷隨機性的模型,先取得實際晶圓的尺寸與切割方式,再利用Matlab模擬,並以隨機產生缺陷的方式而得到的特徵晶圓圖,並將晶圓圖參數化以取得兩個特徵參數NBD (Number of Bad Die,瑕疵晶粒總數)、NCL (Number of Contiguous Line,瑕疵晶粒連續線總數),並將此兩個特徵參數正規化而得到BD與CL。根據不同的BD,模擬大量的合成特徵晶圓圖,產生完整的迴力棒特徵圖(Boomerangs Chart),並以B-score作為判斷晶圓圖隨機性的標準,若得到的結果在迴力棒的基準曲線之外,則可判斷該片晶圓有很大的機率為非隨機缺陷。
    最後綜合此兩類方法,運用類神經網路來判斷錯誤的空間樣態類型,再運用良率與B-score,從隨機性的觀點進行晶圓圖分割分析。除此之外,最後亦可藉由晶圓圖的重疊分析來判斷該產品是否有共同的特徵。;In this paper, we use two methods to analysis wafer map. The first method uses deep learning to train a neural network model by actual wafer map data, which is the WM-811K wafer database released by TSMC. The failure patterns can be divided into the following nine categories: Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near-full, Random, none. Therefore, the trained neural network model can be used to recognize these nine error patterns.
    The second method establish a model for judging the randomness of wafer map spatial pattern. First, obtain the wafer format, and then use Matlab simulation to randomly generate the synthetic wafer map. We extract two parameters NBD (Number of Bad Die), NCL (Number of Contiguous Line), and normalize these two parameters to obtain BD and CL. According to different BD, simulate a large number of synthetic wafer maps, generate a complete Boomerangs chart, and use B-score as the criterion for identifying the randomness of the wafer map.
    Finally, the two types of methods are combined. The pattern recognition model is used to identify the failure pattern. The B-score and the yield are used to further analyze the wafer after partition from the viewpoint of randomness. In addition, the superposition analysis of the wafer map can be used to determine whether the product has common features.
    Appears in Collections:[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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