索引調變(Index modulation)被認為是下一代重要的調變技術，利用了新的維度傳送資料增加頻譜效率(spectral efficiency)。在索引調變裡最為知名的是空間調變(spatial modulation)，空間調變只選擇部分天線傳送數據，減少了天線之間的干擾。通用型籬笆碼空間調變(trellis coded generalized spatial modulation, TCGSM)就是結合了空間調變和迴旋碼(convolutional coded)，並使用維特比演算法(Viterbi)解調並達到最大相似(maximum likelihood)結果。論文中主要探討如何將球面解碼(sphere decoding)與維特比演算法結合以實現軟決策(soft decision)，改變迴旋碼的編碼率使空間維度(空間維度)和星座圖的位元錯誤率(bit error rate)平衡，讓整體效能提高。考慮硬體實現使用了簡化型球面解碼(reduced sphere decoding)來減少球面解碼的硬體複雜度，以及減少序列長度(sequence length)以降低維特比演算法的記憶體數量，效能只劣化了大約0.4 dB。硬體方面則設計支援2根接收端天線，因為空間調變的特性，傳送端天線可以支援8至32根。硬體可以支援三種編碼率以及16QAM和QPSK共6種組合。以TSMC 40nm製程設計晶片，根據佈局後模擬數據顯示，最高時脈速度可達139.5 MHz，core面積1 mm^2，最大吞吐量可以達到5 Gbps，功率消耗161 mW。;Index modulation is regarded as a promising modulation scheme for the next generation wireless communications. Because index modulation conveys digital data in the new domain, the spectral efficiency is increased. Spatial modulation is the most well-known style of index modulation. Spatial modulation conveys digital data by using part of the transmission antennas, thus reduces the inter-antenna interference. TCGSM combines convolutional coded and spatial modulation, and uses Viterbi decoder for maximum likelihood detection. In this paper the detector relying on the soft decision by combining the Viterbi decoder and sphere decoding is implemented. In order to improve overall performance and balance the bit error rate of spatial domain and constellation, multiple convolutional coded code rates are used. To facilitate hardware design, we use k-best to reduce the complexity of sphere decoding, and change the constraint length to reduce the number of memories of the Viterbi decoder. Although BER is degraded about 0.4 dB, hardware complexity can be reduced over 70%. The hardware supporting 2 receiver antennas is designed. There exists only the minimum requirement for the number of transmitting antennas because of the characteristics of the spatial modulation. Our design can support 3 code rates and two kinds of constellations including 16QAM and QPSK, a total of six combinations. The hardware is implemented in TSMC 40nm CMOS technology. According to the post-layout simulation, the maximum operating frequency achieves 139.5 MHz. The core area is 1 mm^2, and the maximum throughput can be up to 5 Gbps and the power consumption is 161 mW.
