良率和隨機均勻性檢定在晶圓圖分析中的應用;Applications of Yield and Randomness Homogeneity Tests to Wafer Map Analysis

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Title:	良率和隨機均勻性檢定在晶圓圖分析中的應用;Applications of Yield and Randomness Homogeneity Tests to Wafer Map Analysis
Authors:	吳承晏;Wu, Cheng-Yan
Contributors:	電機工程學系
Keywords:	晶圓圖;良率均勻性;隨機性;均勻性;標準差;Wafer map;Yield homogeneity;Randomness;Homogeneity;Standard deviation
Date:	2020-01-20
Issue Date:	2020-06-05 17:39:57 (UTC+8)
Publisher:	國立中央大學
Abstract:	晶圓的測試需要耗費人力與時間，找出一個快速檢測錯誤的方法是必然的。本研究的目的是將晶圓均勻度進行另一種方式的探討，利用均勻性的檢定來篩選出隨機性或良率不均勻的晶圓，以達到快速檢測的效果。本研究藉由〔1〕矯正後的參數B-Score以及本研究的標準差公式進行隨機性與良率均勻度的判別，標準差公式為經由新撒點模擬方式得出迴旋陀螺圖(Rattleback)後，計算所得。依此公式可應對不同晶粒數量、不同良率的結果計算對應標準差，進而篩選異常晶圓。此前已有論文將晶圓進行切割以做判別，如〔2〕將各晶粒數量各模擬一個運算基底後進行判別以及〔3〕均勻性檢定是以良率差為判別依據。本研究將應用統計學，進行切割部分的均勻度檢定，使用兩種方式分割成兩部分進行驗證，分別是上下切及左右切的方式。檢定方法是將兩部分各計算出特徵參數後，帶入各自的檢定式，檢定分數越高則表示越不均勻，可篩選出具有特殊特徵的晶圓。本研究對隨機性與良率分別建立一個均勻度的檢定，最後使用TSMC提供之WM-811K資料進行檢定驗證，觀察檢定分數最大的幾片，均可見到呈現明顯錯誤特徵。本文將會使用兩種模式來進行均勻性測試，分別為分割晶圓以及晶圓對晶圓，並呈現結果。所使用的模擬軟體為Matlab。 ;Testing wafers requires manpower and time. Finding a way to quickly detect errors is inevitable. The purpose of this study is to explore another way of wafer homogeneity, and use the verification of homogeneity to screen out wafers with inconsistent randomness or inconsistent yield to achieve the effect of rapid inspection. This study uses 〔1〕 corrected parameter B-Score and the standard deviation formula of this study to determine the randomness and yield homogeneity. The standard deviation formula is calculated from the Rattleback obtained through the new scattering point simulation method. According to this formula, the corresponding standard deviation can be calculated for the results of different numbers of diesize and different yields, and then abnormal wafers can be screened. Previously, there have been papers for dicing wafers for discrimination. For example, 〔2〕 discriminate after simulating each substrate with a variety of diesize, and 〔3〕 the homogeneity test is based on the difference in yield. This study will use statistics to test the homogeneity of the cut part, and use two methods to divide it into two parts for verification, which are the up and down cut and left and right cut. The verification method is to calculate the characteristic parameters of each of the two parts and bring them into their own verification formulas. The higher the verification score, the more inconsistent it is, and the wafers with special features can be screened. In this study, a homogeneity test was established for randomness and yield. Finally, WM-811K data provided by TSMC was used to verify the test. Observing the pieces with the highest test scores showed obvious error characteristics. This paper will use two modes for homogeneity testing, namely wafer partition and wafer-to-wafer, and present the results. The simulation software used is Matlab.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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