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    題名: 一個4x4磁場感應器陣列設計與實作;Design and Implementation of a 4x4 Magnetic field Sensor Array
    作者: 林俊宏;Lin, Chun-Hung
    貢獻者: 通訊工程學系在職專班
    關鍵詞: 異向性磁阻;感測器陣列;磁場成像;Anisotropic magnetoresistance (AMR);sensor array;magnetic field imaging
    日期: 2021-10-22
    上傳時間: 2021-12-07 12:38:35 (UTC+8)
    出版者: 國立中央大學
    摘要: 磁場感測器最早運用於礦物儲量以及地質結構的探勘,隨著物聯網的發展,對感測精確度以及小型化需求越來越高。開發多個單點感測器所組成磁場感測器陣列藉此取得空間中磁場分布的磁場特徵圖像,是非破壞性檢測(NDT)的研究重點。本文主要研究改良以微控制器(MCU)作為磁場感測器陣列系統控制核心所造成的傳遞延遲性及不同步問題。藉由MIAT實驗室所提出系統設計方法論設計一磁場感測陣列平行控制器,運用FPGA平行處理特性同步接收磁場感測器陣列資料,解決感測器與微控制器之間傳輸延遲性及不同步情況下影響獲取磁場數據的精確度,同時解決應用在複雜磁場感測器陣列系統開發時,微控制器會遇到的硬體資源不足問題。功能驗證上實作磁場感測器與FPGA嵌入式平台硬體電路板設計,組成4x4磁場感測器陣列系統。並於此系統進行實驗。實驗結果證明,利用FPGA所設計之平行控制器做為磁場感測器陣列系統控制核心,傳輸速度上16顆感測器所組成磁場感測器陣列磁場分量數據約4ms能完成擷取,相較於微控制器架構傳輸速度能縮短10倍的時間,有效降低傳輸延遲性提高磁場數據的精確度,並基於此系統架構實現磁場感測器陣列動態磁成像系統實作。;Magnetic field sensors had first used in the exploration of mineral reserves and geological structures. With the development of the Internet of Things (IoT), the requirements for sensing accuracy and miniaturization are getting higher and higher. The magnetic sensor array for spatial magnetic field distribution image is an important research area for non-destructive testing (NDT). This article mainly studies and improves the transmission delay and asynchronous issues caused by the microcontroller (MCU) in the magnetic field sensor array system. According to the system design proposed by the Machine Intelligence and Automation Technology (MIAT), the parallel controller in the magnetic field sensor array with Field Programmable Gate Array (FPGA) is used to receive the data synchronously. This design also solved the problem of insufficient hardware resources. At the same time, we solve the issue of transmission delay between the sensor and the microcontroller with more accurate magnetic field data under asynchronous conditions. We designed a 4x4 magnetic field sensor array system with FPGA in a plastic circuit board (PCB). Based on the implementation of the FPGA system architecture, we achieve the data from 16 sensors can be received within 4 ms. Compared with the design of single-chip architecture, the transmission speed decreased by 10 times. We successfully improve the transmission delay and the accuracy of sensing data.
    顯示於類別:[通訊工程學系碩士在職專班 ] 博碩士論文

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