| 摘要: | 一般常見的三閘極(tri-gate)結構氮化鎵增強型金絕半場效電晶體為了達到正的臨界電壓，需要設計奈米尺寸的鰭寬度(WFin)，來有效控制通道達成增強型工作，而製程則需要奈米等級曝光。本論文研究主要探討掘入式(gate recess)三閘極氮化鎵增強型金絕半場效電晶體，三閘極結構設計為在閘極金屬下方蝕刻微米等級的數個並列溝槽(trench)，進而定義鰭式(fin shaped)溝道並提高閘極控制能力，再搭配氮化鋁鎵能障層的完全掘入確保元件為常關型操作，並同步製作掘入式平面金絕半場效電晶體進行電性比較。
在電晶體製作方面，使用高臺蝕刻與離子佈值兩種不同元件隔絕方式進行元件製作研究。元件藉由離子佈值絕緣後，當經過ICP進行溝槽挖掘後，額外使用稀釋的BOE、HCl 溶液和氫氧化四甲基銨(TMAH)處理清潔蝕刻表面，再透過原子層沉積(ALD) 沉積20 奈米的氧化鋁(Al2O3)當作閘極絕緣層。最後完成的元件具有1.2 m的溝槽寬度，0.8 m的鰭寬度。元件的最大增益轉導值、最大汲極電流值、最小次臨界擺幅、導通電阻、元件關閉時的漏電流方面，皆是掘入式三閘極氮化鎵增強型金絕半場效電晶體比掘入式平面元件之特性好，呈現出掘入式(gate recess)三閘極結構的優勢。掘入式三閘極金絕半場效電晶體具有2.5 V的臨界電壓、1121 mA/mm 的高汲極電流和2×10^8的電流開關比。且由遲滯效應去估算介面缺陷密度，跟量測電容使用電導法萃取界面缺陷密度有相似的趨勢，就是元件經過額外稀釋的BOE、HCl 溶液和氫氧化四甲基銨(TMAH)處理蝕刻表面可以改善介面缺陷密度。得到在介電層與半導體的界面，界面缺陷密度約為4×10^12 eV-1cm-2。此研究結果證實了微米等級的溝槽搭配掘入式製程可以呈現三閘極結構的氮化鎵元件。
;In order to reach positive VTH in basic tri-gate devices, it is necessary to design nano-level fin-width (WFin) to effectively control the channel to achieve enhancement mode operation, and requires nano-level exposure accuracy. In this work, a normally-off Recessed tri-gate MIS-FET is fabricated and characterized. The Recessed tri-gate MIS-FET in this work is fabricated by micro-level trenches, which are used to define the fin-shaped channel and improve the gate control capability. Even with a micrometer trench width (WTrench), as long as the AlGaN barrier recessed completely under the gate metal, a normally-off recessed tri-gate GaN MIS-FET is achieved. For comparison, standard Recessed planar MIS-FETs were also fabricated using the same process flow on the same chip.
In terms of devices processing, two different device isolation methods, mesa isolation and ion implantation, are used for fabrication. After device are isolated by Ar-ion implantation and are etched trenches by ICP, the recessed surface is cleaned by a diluted BOE, HCl solution, and TMAH treatment before a 20 nm Al2O3 deposition by ALD. Finally, the finished Recessed tri-gate MIS-FET has a WTrench of 1.2 μm, and WFin of 0.8 μm. In I-V measurement, gm,max, ID,max, S.S., RON, and leakage current at off state of Recessed tri-gate MIS-FETs are better than Recessed planar MIS-FETs, which presents the advantages of tri-gate structure. Recessed tri-gate MIS-FET demonstrates a high threshold voltage of 2.5 V, a high drain current of 1121 mA/mm, and an on/off current ratio of 2×10^8. Besides, the devices show a low I-V hysteresis. A hysteresis effect in device I-V characteristics is used to estimate the interface state density(Dit), which is similar to the conductance extraction result in C-V measurements. That is, the device is cleaned by a diluted BOE, HCl solution, and TMAH treatment can improve the interface state density. The C-V measurement was carried out and the Dit distribution at different energy levels was about 4×10^12 eV-1cm-2. All experimental results confirm of combining micro scale trenches to form tri-gate structures and gate recess design can achieve high performance normally-off GaN transistors. |
