本論文為探討增強型氮化鎵高電子遷移率電晶體(HEMT)的不同閘極偏壓特性研究，根據閘極的操作方式，分成以下兩個部分討論：(1)蕭特基p-GaN閘極氮化鎵電晶體之閘極於高正偏壓下的崩潰機制與機制分析；(2)不同閘極結構商用氮化鎵電晶體之閘極於零伏與浮接狀態下之漏電流比較和原因探討。 現今商用的蕭特基p-GaN閘極氮化鎵電晶體主要的閘極操作偏壓一般來說不超過7 V，由於過高的閘極偏壓將引發高電場效應並造成閘極蕭特基電極與氮化鎵的界面退化。本論文著重在分析不同閘極偏壓下的崩潰機制，透過施加不同的閘極偏壓與環境溫度，探討閘極漏電流的變化。並利用韋伯分布以評估元件可於十年操作前提下的閘極偏壓大小。另進行閘極階段式量測，得到閘極在不同連續偏壓量測下的穩定性。觀察到當閘極於不同高正偏壓條件崩潰後，閘極漏電流會呈現如電阻或二極體般的電性，關於其崩潰後的電性現象，本研究提出等效電路模型進行剖析，主要崩潰原因來自於閘極和源極之間的耐壓性。 論文中另一種研究閘極操作方式為浮接(floating)，透過量測各種商用增強型氮化鎵電晶體在閘極浮接時的基本電性，觀察到當閘極浮接時，元件端點(汲極-源極間)持續增加偏壓下會產生極高的電晶體關閉漏電流。通過比較閘極在零伏與浮接下的電流值，推測在VDS偏壓時，閘極與汲極間的電容會於閘極浮接狀態下產生充電效應，並使載子累積於閘極p-GaN層內，導致元件的開啟使汲極-源極間漏電流(ID)增加(可高達1 mA)。而閘極在零伏下的電流值仍維持在正常的電晶體關閉狀況範圍(10^-10 ~ 10^-11 A)。 ;In this study, the gate characteristics of the enhancement-mode AlGaN/GaN high-electron-mobility transistors (HEMTs) has been widely investigated. Based on the gate operation method, it is divided into the following two different section: (1)The gate breakdown mechanism and electrical analysis of Schottky p-GaN Gate HEMT under high positive bias (2) Comparison of the electrical properties of the commercial GaN-based transistors with different gate structure under zero gate bias and gate floating. Nowadays, the gate operation bias of commercial p-GaN Gate HEMT does not exceed 7 V, because the excessive gate bias will induce high electric field and damage the interface between gate metal and p-GaN layer. This thesis is focused on analyzing the breakdown mechanism through applying different gate bias and various ambient temperature, to observe gate leakage current variety. Afterwards, use numerical method of Weibull distribution to estimate the gate bias after ten years operation. Then, the gate-step stress measurement is also adopted, to obtain the stability of the gate control with continuous gate bias measurement. When the gate breakdown, the change of gate leakage current before and after high voltage stress is observed. The gate leakage current will present like a resistor or a diode after gate breakdown, so the equivalent circuit has been proposed to explain this phenomenon, indicating that the reason of gate breakdown is from the stability between gate and source electrode. This study also demonstrates the I-V behaviors of various commercial E-mode GaN-based transistors under gate floating and zero gate bias. The high off-state drain current is observed when continuously increase the drain bias under gate floating. Through comparing the current with gate floating and zero gate bias, it is suspected that the capacitance that between gate electrode and drain electrode will charge during the gate floating measurement. The charging effect will induce the carrier accumulate in p-GaN layer, and result in high off-state drain current.
