| 摘要: | 近年來，矽基的氮化鋁鎵/氮化鎵高電子遷移率電晶體以高載子遷移率、耐壓高溫、高載子濃度以及寬能隙的優勢漸漸取代傳統矽元件。然而為了得到更好的氮化鎵品質就必須要克服矽基板與氮化鎵的晶格常數差、熱膨脹係數不同所產生的缺陷，例如：螺旋差排、刃差排，以及晶片翹曲與龜裂的問題。特別是當要提高元件的崩潰電壓時，磊晶層的厚度就需要增加，其晶片翹曲與龜裂問題就更加嚴重。為了解決上述問題。此研究選用超晶格做為氮化鎵緩衝層，因超晶格緩衝層不僅僅能夠降低磊晶層中的差排密度，也具有控制晶片翹曲的功能，能夠達到更高的垂直崩潰電壓與氮化鎵薄膜品質。
本論文的研究主題是探討有機金屬氣相磊晶成長氮化鋁鎵/氮化鎵高電子遷移率電晶體(AlGaN/GaN HEMT)於矽基板之過程中，磊晶片翹曲的機制與控制方法。本研究藉由不同超晶格緩衝層的結構，包括鋁成分、厚度與對數，來控制磊晶層曲率變化，以避免磊晶薄膜龜裂並降低晶片翹曲。實驗結果與Stoney formula數學模型之結果大致相符；另亦與商用STREEM軟體所模擬出來的結果比較，發現緩衝層中超晶格的週期數與其組成亦須在應力控制時列入考量。
透過此研究所得之模型與設計原則，為獲得更大的壓縮應力，將超晶格的組成從Al0.24Ga0.76N 11 nm/AlN 5.4 nm 優化成Al0.3Ga0.7N 14 nm/AlN 5.2 nm，並將超晶格週期數從30對減少至20對，其中透過Stoney formula所計算κ的總和從-0.58 km-1增加至-0.87 km-1。此外，優化後的實驗曲率從每對中-0.24 km-1變為-0.37 km-1，這代表著優化後的超晶格緩衝層產生比原始緩衝層更高的壓應力。最後在不犧牲晶圓翹區程度下，成功地減少磊晶成本並將磊晶片邊緣龜裂範圍從3-5 mm減少至2-3 mm，有效增加晶圓可用面積。
;In recent years, wide bandgap AlGaN/GaN-on-Silicon high electron mobility transistors (HEMTs) have gradually replaced traditional silicon devices because of their high carrier mobility, high breakdown voltage, high temperature operation and high carrier concentration. However, the performance of GaN HEMTs is still far from its theoretical limits, mostly because of the unavailability of native GaN substrate, resulting in high defect density in the epilayer, such as threading dislocation density, which is typically above 109 cm-2. Wafer bow and/or cracking due to large lattice and thermal mismatch between the silicon substrate and the GaN epilayer is still a concern that needs to be addressed. Additionally, wafer bow could be even serious when the total thickness of the epilayer increases beyond 5 m, which renders the vertical breakdown voltage of the device. Stress relief buffer layer beneath the GaN buffer is often used to minimize the strain caused by the lattice mismatch between the epilayers. Several stress relief buffer layers have been proposed in the past. Nonetheless, graded AlGaN, superlattice (SL) buffers or even the combination of both is most commonly used in modern GaN-on-Si heterostructures. Superlattice buffers in this regards may provide more degree of freedoms, which not only reduces the density of dislocation in the epitaxial layer, but also has the ability to control the wafer bow precisely, resulting in thicker epilayer to achieve higher vertical breakdown voltage. However, the design of superlattice buffer is not straightforward as it involves a number of design parameters, such as the layer composition, thickness, superlattice periods, and position in the buffer. Therefore, it is still a research field of interest.
The present study aims to explore the design and physics of stress control mechanism of AlGaN/GaN HEMTs on silicon using superlattice stress relief layers. To achieve this, we adopted different superlattice buffer layers. For example, we used different aluminum compositions, thicknesses, and periods. The results are consistent with the mathematical Stoney formula. In addition, when compared to the simulated values obtained by a commercial software package, STREEM, we found that the number of SL periods and composition should also be taken into account when controlling the stress during buffer layer growth. Further, in order to allow the superlattice buffer layer to generate more compressive stress through the above method and to maintain the equivalent aluminum composition of the superlattice buffer layer at 50%, the composition was changed from Al0.24Ga0.76N 11 nm/AlN 5.4 to Al0.3Ga0.7N 14 nm/AlN 5.2 nm. The corresponding sum of curvature (κ) calculated from the Stoney formula increases from -0.58 km-1 to -0.87 km-1. Also, the experimental curvature changes from -0.24 km-1 to -0.37 km-1 in each pair, which means that the superlattice buffer layer generates a higher compressive stress than the original one.
In conclusion, our results demonstrated that the SL composition, thickness, and the number of periods need to be optimized to achieve crack-free thick GaN layers on Si. By applying the model developed by the present study, decreasing the SL period from 30 to 20 periods, and optimizing the composition, the edge cracking range of the epilayer on a 150 mm Si substrate could be successfully reduced from 3-5 mm to 2-3 mm, which increases the useable area of the wafer. |
