未來世代走向5G的通訊系統，巨量多輸入多輸出系統(Massive MIMO system)被認為是具有潛力的技術，提供了更高的系統容量。而隨著基地台所制定天線數量的增加，更為複雜的均勻矩形陣列(Uniform rectangular array, URA)的二維天線系統逐漸發展而出，系統也必須承受更高的計算複雜度，傳輸過程的通道效應影響訊號的偵測，因此通道估測便成為一個相當重要的課題。常見以特徵分解(Eigen decomposition)與壓縮感知(Compressed sensing, CS)為基礎進行估測，需要使用矩陣分解或是反矩陣運算而導致相當高的運算複雜度，於是離散傅立葉轉換(Discrete Fourier transform, DFT)為基礎的通道估測法開始被採用，透過傅立葉轉換將通道換至角度域並偵測所需的通道狀態資訊。本論文以離散傅立葉轉換法為基礎進行通道估測，為了節省運算複雜度，我們提出階層式內插法，針對目標區域於空間頻譜進行小範圍的內插，逐步提升局部空間頻譜解析度來估測角度資訊，捨棄估測過程中無用的運算量；除此之外，利用於空間頻譜得到的角度資訊，消除來自其他傳輸路徑的能量干涉，提升通道增益的估測準確度，由於消除干涉的運算過程中需進行反矩陣運算，提出重要路徑優先的方式降低反矩陣運算時的矩陣大小。本次所提出的演算法與墊零法(Zero-padded)、旋轉法(Phase-rotated)相比減少更多運算量並提升通道估測效能。在硬體設計方面則針對墊零法設計32點快速傅立葉轉換的硬體架構，因為墊零法的輸入包含許多的零元素，利用此特性來降低架構中前端的硬體消耗，最後採用並列輸入之混合radix-2和radix-4的多路徑延遲交換線路系統(Multi-path delay commutator, MDC)架構實現。;For systems equipped with uniform rectangular antenna array, two-dimensional fast Fourier transform (2D-FFT) is often employed to transform the information in the spatial domain to the angular domain. In this thesis, based on the discrete Fourier transform method, a low-complexity approach for channel estimation is developed. To save the computational complexity, the hierarchical channel interpolation algorithm is proposed. Local interpolation with fine resolution is only applied to the selected regions for obtaining required angular information to eliminate the unnecessary computations. Furthermore, we can eliminate the path interference from due to the energy leakage according to the information of the virtual angle that is obtained from the spatial spectrum and can improve the estimation accuracy of the channel gain. However, the matrix inversion is needed during the process for interference removal. In order to reduce the size for matrix inversion, only the critical paths with stronger path gains are considered. Compared with the conventional zero-padded and phase-rotated methods, the proposed algorithm reduces about 50%~90% complexity when searching direction of angles and improves the channel estimation performance. As to the hardware design, a 32-point fast Fourier transform (FFT) hardware architecture is designed for the zero-padded 2D-FFT method. Because a half of input data are zero, we can exploit the property and eliminate the unnecessary arithmetic units. Finally, the mixed radix-2 and radix-4 MDC architecture with parallel inputs is adopted to be implemented for 32-point FFT.
