考慮電壓衰退和繞線影響以優化電路時序之電源供應網絡精煉策略;Power Distribution Network Refinement for Timing Optimization Through IR-drop and Routing Trade-off

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/88379

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/88379

Title:	考慮電壓衰退和繞線影響以優化電路時序之電源供應網絡精煉策略;Power Distribution Network Refinement for Timing Optimization Through IR-drop and Routing Trade-off
Authors:	張弘翰;Chang, Hung-Han
Contributors:	電機工程學系
Keywords:	實體設計;晶片內電網;壓降效應;繞線壅塞;Physical Design;Power Distribution Network;IR-drop;Routing Congestion
Date:	2022-04-27
Issue Date:	2022-07-14 01:08:55 (UTC+8)
Publisher:	國立中央大學
Abstract:	在晶片設計中，電路藉由晶片內電網供應電壓源和接地，而在設計晶片內電網時需要考慮到壓降反應(IR-drop)對晶片效能所造成的影響。壓降反應(IR-drop)發生由於在電源流的傳遞過程中，因為傳遞電源的導線本身具有電阻值，此電阻值會使電源值下降，而形成壓降反應。在晶片設計中，如果晶片內電網發生大量的壓降反應，將會降低電路的抗雜訊能力，甚至影響到電路的效能。先前有許多關於解決壓降反應的相關研究，其中一個方法為在設計晶片內電網時即考量壓降影響，並設法透過優化晶片內電網設計來減低壓降反應。另一方面，在晶片內電網的設計中，電源導線本身需要消耗繞線資源，此外，在晶片內電網設計中，我們會需要藉由導通孔陣列(via arrays)來將電壓供應至底層電路，而這些導通孔也會佔據電路的繞線資源，進而影響電路繞線的複雜度而導致繞線壅塞。繞線壅塞也會影響電路的效能並增加電路設計的時間，所以必須在設計晶片內電網時須考慮到訊號線繞線的問題。在本篇論文中，我們同時針對上述的壓降效應和繞線問題進行考量，並提出一優化晶片內電網設計來優化電路的時序及效能。具體而言，我們提出一完整的晶片內電網的精進架構，透過在原本晶片內電網中適當的添加額外的供電導線，來優化電路之時序與效能。我們透過成本函數來反應電源導線對於電路時序的影響，並藉由成本函數來找出適當的晶片內電網結構。相較於先前的研究，我們同時考慮到壓降反應和繞線影響來優化我們的電路時序。研究結果顯現，相較於優化前的電路，我們能達到5.6%的總負時序量優化，並能達到36%的壓降效應。 ;Power networks which provide supply voltage and ground to transistors are essential for modern ICs. It is necessary to consider IR-drop when constructing power network. The IR-drop occurs during the transfer of the supply voltage from the power network to the circuit. The wires of the power network contain parasitic resistance which will lead the dropping of supply voltage. If a large amount of voltage drop occurs on the power network in a circuit, the noise margin of the circuit will be reduced, and the performance of the circuit will be degraded. In previous researches, the researchers designed an IR-drop-friendly power network to reduce the IR-drop of the circuit. On the other hand, the wire of the power network consumes the routing resources. Moreover, the power stripes connect to the underlying circuit through the via arrays. The via arrays also occupy the routing resource, thereby increasing the complexity of the circuit routing and causing routing congestion. Therefore, it is necessary to consider the routing issue when designing the power network. In this work, we propose a power network refinement framework which can generate appropriate power network structure for better circuit timing by considering both IR-drop and routing congestions. In our framework, we add additional power stripes based on the initial power network to improve the circuit timing. We use a cost function to analyze the relationship between circuit timing and IR-drop as well as routing congestions, and add the power stripes based on the cost function evaluation. The experiment result shows that we can improve the total negative slacks of the circuit by the 5.6% compared to the original design. Also, we can save the 36% of the IR drop compared to the original design.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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