本論文研究內容以FPGA硬體架構設計與實現DVB-S2發射機與接收機，在發射機中，包含了BCH code、LDPC code和調變器，並增加了適應編碼調製（Adaptive Coding and Modulation，ACM）機制，使發射機在切換調變時更加穩定，接收機則包含時間同步、頻率同步、相位同步，時間同步採用內插器，以消除時序偏移並進行同步取樣，頻率同步則是以固定星座圖去計算及修正頻率偏移，相位同步則是以已知的Start Of Frame (SOF) 來修正相位，並增加自動偵測調變機制 (MODCOD-Detector) ，以便後續解碼器所用，將其整合，使其實現實際DVB-S2收發機。 ;Digital Video Broadcasting-Satellite-Second Generation (DVB-S2) is one of the satellite broadcasting standards. Compared with Digital Video Broadcasting-Satellite (DVB-S) , Digital Video Broadcasting-Satellite-Second Generation has an improved transmission capacity. In addition to QPSK, it also provides 8PSK, 16APSK, 32APSK, and other modulation methods. It is more suitable for satellite transmission channels with relatively poor linear characteristics. The main purpose of the paper is based on FPGA hardware architecture to design and implement DVB-S2 transmitter and receiver. In the transmitter, using BCH code, LDPC code and modulator. And added the Adaptive Coding and Modulation ( ACM ) to make the transmitter more stable when switching modulations. The receiver includes timing synchronization, symbol synchronization, and phase synchronization. And increase the automatic detection modulation (MODCOD-Detector). Make it an actual DVB-S2 transceiver.
