| 摘要: | 在本篇論文中，我們提出一個可應用於有線電視上的載波及時序回復電路架構 : 不只適用於垂直正交振幅調變 (QAM, Quadrature Amplitude Modulation)，同時也適用於殘旁邊帶振幅調變 (VSB, Vestigial Sideband Modulation)，並且以很少的硬體代價實現之。在載波回復電路中，我們以驟斜率方法 (Steep Gradient Method) 來實現電路所需的相位檢測器 (Phase Detector) ；而在時序回復電路中，我們則使用鮑率 (Baud-Rate) 相位檢測器。此外，為了簡化電路的實現，我們另外採用了方向理論 (Sign Algorithm)，使得原來電路中的乘法器可以用二補數電路來取代。為了增加載波回復電路的頻率追蹤範圍 (Acquisition Range)，在垂直正交振幅調變模式中，我們加入了一對相位解旋/旋轉電路 (Derotator/Rotator Pair) 於載波回復電路之前；而在殘旁邊帶振幅調變模式中，我們另外加入一個鎖頻迴路 (Frequency Locked Loop)。另外，我們還利用纜線通道模型（Cable Channel Models）來模擬有線電視纜線的傳輸效應。為了使載波回復電路能抵抗纜線的傳輸雜訊，在殘旁邊帶振幅調變模式中，我們重新調整鎖頻迴路的參數值以改善穩態時的誤差；在垂直正交振幅調變模式中，我們則採用切換載波回復路徑的方式來解決等化器箝制載波回復電路的頻率追蹤範圍的問題。如此，依據C語言所架構的系統模擬結果，載波回復電路具有±100KHz的頻率追蹤範圍。最後，我們將鎖頻迴路、載波回復電路、時序回復電路、數值控制震盪器(NCO, Numerically Controlled Oscillator) 以及混波器 (Mixer) 以硬體描述語言Verilog來描述，並以Synopsys做電路的整合與最佳化。根據整合後的結果顯示，整個電路總共需要24,531閘。 In this thesis, an architecture design and hardware implementation of the carrier recovery (CR) and timing recovery (TR), which is suitable for both Vestigal SideBand Modulation (VSB) and Quadrature Amplitude Modulation (QAM), in CATV system are proposed. The proposed CR adopts a Steep Gradient mothod, while the proposed TR em-ploys a baud-rate TR in our system. To reduce the hardware complexity, both of them use sign algorithm. Furthermore, to increase the acquisition range of CR, a Frequency Locked Loop (FLL) is used in VSB mode, while a derotator/rotator pair is adopted in QAM mode. As a result, the CR can reach ±100KHz acquisition range from simulation results when using the ideal-like channel model with a little intersymbol interference (ISI). Besides, for enhancing the CR to fit all the feasible cable channel models, the filter of the FLL was re-designed in VSB mode. The filter coefficients have been modified that deamativally reduce the hardware complexity. Moreover, the control of rotator/de-rotator to switch the CR loop during different stages are used to enhance the performance of the CR and the EQ in QAM mode. Finally, the whole design, which consists of a mixer, a FLL, a CR, a TR, a loop controller and two NCOs, is desribed with Verilog hardware language and synthesized by Synopsys. From synthesis reports, the total gate counts are 24,531 gates. |
