| 摘要: | 在這篇論文中, 我們對Booth編碼的蒙哥馬利乘模運算理論提出一種設計方法, 這種新的方法能引導我們將RSA密碼系統的加密解密的所需迴圈數減少. 另外, 再加上我們將管線處理以及折疊與展開的技巧應用在蒙哥馬利乘模運算模組的設計上, 我們設計出一個基本運算單元, 簡稱蒙哥馬利單元, 由此, 我們用疊接不同的蒙哥馬利單元數目並重覆利用可以很容易的改變我們的RSA晶片的設計以符合不同的要求, 最後, 經過我們最佳化之後的設計結構, 是一個數位循序的, 純時脈性的,可疊接的, 且模組使用效率為百分之百的結構. 模擬結果顯示, 在同樣用H algorithm的情況下, 我們做RSA運算所需的迴圈數由2n 降到 n, 此外, 我們也降低了硬體複雜度, 整體的效率約為前人設計的2.5倍, 而RSA晶片的加解密模擬速度最高可達到476kbit/sec左右. In this thesis, a design methodology for Booth-encoded Montgomery's modular multiplication algorithms is proposed. The new design methodology helps us to re-duce the required iteration number in the Encryption/Decryption of RSA cryptosys-tem. With application of pipelining and folding/unfolding techniques to the design of Montgomery's modular multiplication module, we construct the processing element (PE) called M-cell. With the M-cell's, we can easily reconfigure the RSA chip. It is very convenient to reconfigure the RSA chip for different specification by cascade different number of M-cells and reuse them. The final optimized Montgomery's modular multiplication module is a digit-serial, pure-systolic, and scalable architec-ture with 100% utilization of all PE modules. The simulation result shows that we can not only reduce the required iteration number from 2n^2 to n^2 using H algorithm, hard-ware complexity is also simplified. The efficiency (time-area product) of our design is improved about a factor of 2.5. The simulation results show that the maximum speed-performance of single RSA chip can be up to 476kbit/sec. |
