以改良式向量旋轉器為核心的遞迴式傅立葉模組設計; A Cost-Effective Time-Recursive FFT architecture Based on Improvement Vector Rotator for DMT Transmitter

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Title:	以改良式向量旋轉器為核心的遞迴式傅立葉模組設計;A Cost-Effective Time-Recursive FFT architecture Based on Improvement Vector Rotator for DMT Transmitter
Authors:	俞已立;Chi-Li Yu
Contributors:	電機工程研究所
Keywords:	快速傅立葉轉換;座標旋轉數位計算器;非對稱數位用戶迴路;離散多頻調變技術;FFT;CORDIC;ADSL;DMT
Date:	2000-07-13
Issue Date:	2009-09-22 11:38:26 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	離散多頻調變技術(DMT)是非對稱數位用戶迴路(ADSL)的實體層傳輸標準，它能克服傳統電話雙絞線的傳輸瓶頸，達到高速傳輸速率的要求。但是，高度的運算/硬體複雜度是DMT的主要缺點，而構成調變核心的傅立葉/反傅立葉轉換(FFT/IFFT)模組則特別地複雜。在這篇論文中，我們採用時間遞迴式傅立葉轉換架構來實現DMT發射器裡的反傅立葉轉換模組。為了減少該模組的遞迴次數，我們重新排列組合輸入信號，使得遞迴次數減半，而硬體複雜度也因此得到化減。此外，由於該時間遞迴式傅立葉轉換架構的核心是一個以乘法器為基礎的旋轉器，為使硬體複雜度進一步減少，我們以數位座標旋轉計算器(CORDIC)來取代它。在回顧一些以CORDIC為基礎的旋轉器後，我們選擇使用擴大的基本角度集合CORDIC (EEAS-CORDIC)，因為它具有運算快速的優點。接著我們發展出一套設計流程來減低EEAS-CORDIC裡位移器的面積，根據模擬結果，在透過這套設計流程後，位移的閘數可減少51%，而新型CORDIC的總體雜數則可減低32%。並且，當新CORDIC與修改過的時間遞迴式反傅立葉轉換模組結合後，速度及精確度也都能符合規格的要求。總體來說，上述的改進使得新的反傅立葉轉換模組更適合於超大型積體電路實現。 Discrete Multitone modulation (DMT) is the physical-layer transmission standard of Asymmetric Digital Subscriber Line (ADSL). It can achieve rate-adaptive high-speed transmission over twisted-pair copper lines in telephone carrier serving areas (CSA). But, one major disadvantage of the DMT scheme is its high computational/hardware complexity, especially for the IFFT/FFT operations that form the multitone processing kernels. In this thesis, we employ time-recursive FFT architecture to realize the IFFT module in DMT transmitter. To reduce the iteration number of the time-recursive IFFT, we reorder the input data. Hence, the iteration number is halved and the hardware complexity is reduced, too. Furthermore, we employ Cordinate Rotation Digital Computer (CORDIC) to replace the multiplier-based rotator, which is the original kernel of the time-recursive IFFT. After reviewing some CORDIC-based rotators, we choose Extended Elementary-Angle Set CORDIC (EEAS-CORDIC) due to its high performance of speed. A new design flow is also developed to reduce the hardware complexity of the shifters in EEAS-CORDIC. By going through this flow, the gate count of all shifters is reduced 51%, and overall gate count of new CORDIC is saved 32%. Simultaneously, the speed and accuracy performance can also achieve the specification after combining the modified time-recursive IFFT and the new CORDIC. By the improvements of our work, the new IFFT module is more suitable for practical implementation.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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