在晶圓圖分析中基於特徵擷取分類網格樣態;Feature-based Grid Pattern Classification in Wafer Map Analysis

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题名:	在晶圓圖分析中基於特徵擷取分類網格樣態;Feature-based Grid Pattern Classification in Wafer Map Analysis
作者:	林永琳;Lin, Yung-Lin
贡献者:	電機工程學系
关键词:	晶圓圖;錯誤樣態辨識;特徵分析;Wafer map;Pattern recognition;Feature based analysis
日期:	2022-07-29
上传时间:	2022-10-04 12:04:40 (UTC+8)
出版者:	國立中央大學
摘要:	在本篇論文中，我們提出了以特徵擷取方法的模型來辨識晶圓圖的網格錯誤樣態。我們使用的實際晶圓為台積電所提供的WM-811K晶圓資料庫，其中的錯誤樣態可分為以下九類，Center、Donut、Scratch、Edge-Ring、Edge-Loc、Loc、Near-Full、Random、None。本篇探討的網格錯誤樣態並沒有在以上分類，加上隱藏的網格錯誤樣態難以被人眼判別，因此本篇利用了兩種方法來標記網格錯誤樣態，第一種方法是直接透過人眼判別來標記，第二種方法我們利用了程式輔助挑選出可能的隱藏網格錯誤樣態，再透過人眼判別來標記網格錯誤樣態，值得一提的是，我們在改善網格錯誤樣態辨識模型時同時修正網格錯誤樣態的標籤。　　網格錯誤樣態辨識時，聚類的存在會影響網格錯誤樣態的辨識進而造成誤判，因此在模型的第一步，我們使用了DBSCAN聚類分析算法移除聚類，將晶圓圖上群聚的壞晶粒移除；再來，我們發現直線壞晶粒並不會在第一步中被濾掉，且會造成網格錯誤樣態的誤判，因此模型的第二步我們針對直線壞晶粒做移除；接著，模型的第三步我們要找尋晶圓圖上的網格樣態，我們根據重複出現的方向將網格錯誤樣態分類成列、行和棋盤三種類型，透過行與列兩個方向尋找連續出現的壞晶粒，接著推測是否存在棋盤類型的網格錯誤壞晶粒，在得到列類型、行類型和棋盤三種類型的網格錯誤壞晶粒個數後，透過三種判斷方式識別網格錯誤樣態。　　最後，我們分析模型辨識的結果，並以基於Precision和Recall調和平均的F1-Score當作模型改進的判斷指標。網格錯誤辨識模型的最終版本，F1-Score為74.40%，運算時間約40.07 ms/wafer。;In this paper, we propose a model of a feature extraction method to recognize grid failure pattern in wafer map. The actual wafer we use is the WM-811K wafer database provided by TSMC, and the failure patterns can be divided into the following nine categories: Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near-Full , Random, None. The grid failure pattern discussed in this paper is not classified as above, and the hidden grid failure pattern is difficult to be recognized by human observation. Therefore, this paper uses two methods to label grid failure pattern. The first method is directly label by human observation. In the second method, we use program to collect possible hidden grid failure pattern, and then label grid failure pattern by human observation. 　　In the first step of the model, we use the DBSCAN algorithm to remove the clusters; Secondly, we found that the line defect points will not be filtered out in the first step, and will cause misjudgment of the grid failure pattern recognition, so in the second step of the model, we remove the line defect points; Then, in the third step of the model, we need to find the grid failure pattern on the wafer map. We classify the grid failure pattern into three types: column, row and checkerboard according to the repeated direction. Search for continuous bad dies in both row and column directions, and then speculate whether there is checkerboard type grid failure pattern. After obtaining the number of grid failure pattern of column type, row type and checkerboard type, three judgments are made way to recognize grid failure pattern. 　　Finally, we analyze the results of recognition model, and use the F1-Score as the judgment indicator for model improvement. The final version of the grid failure pattern recognition model, the F1-Score is 74.40%, and the simulation time is about 40.07 ms/wafer.
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