利用石英製程及覆晶技術之100GHz T型貼片天線陣列設計;Design of 100-GHz T-shaped Patch Antenna Array Using Quartz-Sub and Flip-Chip Technology

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Title:	利用石英製程及覆晶技術之100GHz T型貼片天線陣列設計;Design of 100-GHz T-shaped Patch Antenna Array Using Quartz-Sub and Flip-Chip Technology
Authors:	許晉瑄;Hsu, Chin-Hsuan
Contributors:	電機工程學系
Keywords:	覆晶技術;石英製程;貼片天線陣列;太赫茲;Flip-Chip;Quartz Substrate;Patch Antenna Array;Terahertz
Date:	2022-07-29
Issue Date:	2022-10-04 12:04:46 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文提出利用石英製程及覆晶技術之100 GHz T型貼片天線陣列設計。天線陣列由兩層石英基板組成，使用微帶線饋入至C型槽孔，再藉由C型槽孔耦合至輻射貼片產生100 GHz天線輻射模態。採用覆晶方式將兩層石英基板做連結，以達到多層金屬結構需求；使用C型槽孔抵銷電流之特性將背向輻射降低，用以提高天線前後比；使用T型輻射貼片集中電流來提高天線增益。為了縮小初始設計輻射貼片尺寸，在最後分別設計寬度方向及長度方向面積縮小化之天線。寬度方向縮小化天線沿用初始設計，採用挖槽將電流路徑延長達成縮小化；長度方向縮小化天線沿用寬度方向縮小化天線之設計，除了挖槽以外，也在輻射貼片處增加一殘段來延長電流路徑，達成縮小化的目的。本篇論文中天線的設計使用國家研究院台灣半導體研究中心所提供之石英製程製作。整體天線陣列尺寸為22.5×7.5×0.66 mm3(7.5×2.5×0.22 λ03, λ0為100 GHz的自由空間波長)，單一天線元件面積為1.9 mm×1.9 mm。天線陣列量測結果顯示阻抗頻寬13.12%(91.66 GHz-104.53 GHz)，在100 GHz時增益為13.84 dBi，天線前後比為15.01 dB；寬度方向縮小化T型貼片天線面積為1.2 mm×1.9 mm模擬之阻抗頻寬14.76%(94.93-110.06 GHz)，在100 GHz時增益為7.63 dBi，天線前後比為12.79 dB；長度方向縮小化T型貼片天線面積為1.2 mm×1.5 mm，模擬阻抗頻寬17.16%(94.63-112.39 GHz)，在100 GHz時增益為6.02 dBi，天線前後比為14.71 dB。 ;A design of 100-GHz T-shaped patch antenna array using quartz-sub and flip-chip technology is proposed in the thesis. The proposed antenna array consists of two layers of quartz substrates. Using microstrip feeds into a C-slot, then the C-slot couples the signal into the radiating patch. By using the flip chip, two layers of quartz substrates are combined to achieve multi-layer metal structures. The use of C-slot is to offset the current characteristics for reducing the back radiation and then improving the front-to-back ratio of the antenna. In order to reduce size of the patch, the antenna with reduced dimensions in the horizonal and vertical directions are designed. Design of horizontally reduce-sized antenna, following original design, uses slot to extend the current path length to achieve antenna miniaturization; design of vertically reduce-sized antenna, following previous design with slot, uses additional stub to extend current path to attain more antenna miniaturization. The proposed antenna array is realized with the quartz process provided by Taiwan Semiconductor Research Center Institute. Overall antenna array size is of 22.5×7.5×0.66 mm (7.5 λ0×2.5 λ0×0.22 λ0 at 100 GHz), and the single antenna element area is of 1.9 mm×1.9 mm. Measured results of antenna array show that the impedance bandwidth is 13.12% (91.66 GHz-104.53 GHz), gain is 13.84 dBi at 100 GHz, and the front-to-back ratio is 15.01 dBi. The horizontal reduce-sized T-shaped patch antenna area is of 1.2 mm×1.9 mm. Simulated results of antenna show that impedance bandwidth is 14.76% (94.93-110.06 GHz), gain is 7.63 dBi at 100 GHz, and the front-to-back ratio is 12.79 dBi; The vertical reduce-sized T-shaped patch antenna area is of 1.9 mm×1.5 mm. Simulated results of antenna show that impedance bandwidth is 17.16% (94.63-112.39 GHz), gain is 6.02 dBi at 100 GHz, and the front-to-back ratio is 14.71 dBi.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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