積層型三維邏輯電路之性能分析;Performance Analysis of Monolithic 3D Logic Circuits

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題名:	積層型三維邏輯電路之性能分析;Performance Analysis of Monolithic 3D Logic Circuits
作者:	翁承揚;Weng, Cheng-Yang
貢獻者:	電機工程學系
關鍵詞:	積層型三維堆疊;中段製程;後段製程;邏輯電路;Monolithic 3D integration;middle-of-line;back-end-of-line;logic circuit
日期:	2022-08-04
上傳時間:	2022-10-04 12:05:47 (UTC+8)
出版者:	國立中央大學
摘要:	隨著技術節點的演進及製程技術的改良，電晶體及金屬導線可以進一步微縮，並且讓單位面積裡可以容納更多的電晶體，然而隨著面積的微縮，金屬繞線的程度會越來越複雜，因此增加了金屬繞線(Interconnect)的長度，使金屬導線的電阻值也增加，另一方面，金屬導線之間的距離越來越小，金屬導線與金屬導線之間互相耦合的情況便不可忽略。因此本論文利用積層型三維(Monolithic 3D)堆疊技術，以不同三維堆疊設計優化電路特性，研究積層型三維佈局(Layout)對邏輯電路速度的影響。本論文主要探討的邏輯電路包含Inverter、NAND及NOR，利用Synopsys TCAD的Sentaurus Structure Editor (SDE)建立三維結構來分析邏輯電路的特性。論文內容分為三個主題，第一部分介紹本篇論文使用的元件結構-鰭式場效應電晶體以及中段及後段製程金屬導線結構參數。第二部分，本論文利用Transistor-Level積層型三維堆疊來設計邏輯電路，並研究三種Transistor-Level積層型三維堆疊設計，分別是折疊型(Folding)、拼接型(Stitching)及分離型(Separating)，三種設計皆是將N型電晶體放在上層(Top-tier)，P型電晶體放在下層(Bottom-tier)，目的是在製程上可以調整製作流程並獨立優化N型及P型電晶體特性。第三部分是比較Transistor-Level積層型三維堆疊與傳統二維堆疊的邏輯電路，透過積層型三維堆疊重新設計Inverter、NAND及NOR，可以發現不但能縮小邏輯電路的單元(cell)面積，也能減少金屬導線的繞線長度，使邏輯電路的延遲時間(delay time)降低。 ;With the evolution of technology nodes and the improvement of process technology, transistors and metal wires can be scaled down, more transistors can be accommodated in a unit area. However, as the area is reduced, the degree of metal wire routing will become more and more complicated. Since the length of the interconnect metal is increased, the resistance value of the metal wire is increased. On the other hand, the smaller the distance between the metal wires, the metal to metal coupling cannot be ignored. Therefore, this thesis uses the monolithic 3D stacking technology to optimize the circuit characteristics considering different 3D stacking designs. The logic circuits discussed in this thesis includes Inverter, NAND and NOR. We analyze the characteristics of the logic circuit by using Sentaurus Structure Editor (SDE) from Synopsys TCAD to build a three-dimensional structure. In the first part, we introduce the device structure, fin field effect transistor (FinFET), and the metal wire structure parameters of middle-of-line (MOL) and back-end-of-line (BEOL). In the second part, we use the Transistor-Level monolithic 3D stacking technique to design logic circuits, this thesis investigated three Transistor-Level monolithic 3D stacking schemes, including Folding, Stitching and Separating. All the Transistor-Level monolithic 3D stacking schemes in this thesis are designed with N-type transistors on the top-tier and P-type transistors on the bottom-tier. The purpose is to adjust the manufacturing process and optimize the transistor characteristics independently. In the third part, we analyze the logic circuits of Transistor-Level monolithic 3D stacking schemes compared with traditional 2D stacking. The proposed monolithic 3D stacking designs can reduce not only the logic circuit area, but also interconnect length that makes wire routing resistance low and reduces the delay time.
顯示於類別:	[電機工程研究所] 博碩士論文

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