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    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/89967


    題名: 基於模糊派翠類神經網路之微電網太陽能系統低電壓穿越控制策略;Low-Voltage Ride-Through Control Strategy of Solar Energy Generation System in Microgrid Based on Fuzzy Neural Petri Net
    作者: 許祖隆;Syu, Zu-Long
    貢獻者: 電機工程學系
    關鍵詞: 太陽能系統;最大功率點追蹤;電網故障;低電壓穿越;模糊派翠類神經網路;Solar energy generation system;Maximum power point tracking;Grid fault;Low voltage ride through;Fuzzy neural petri net
    日期: 2022-08-09
    上傳時間: 2022-10-04 12:06:02 (UTC+8)
    出版者: 國立中央大學
    摘要: 本論文提出微電網中太陽能系統於正常情況與低電壓故障情況的運作模式與控制方法,正常情況下以最大功率點追蹤太陽能板的功率輸出峰值,並經由DC-AC轉換器將功率傳輸給負載或者回饋給市電;在低電壓故障期間,由規範所規定再生能源裝置於故障期間內提供一定比例之虛功電流補償以輔助市電渡過短暫之電壓低落狀況,並限制於故障時間內斷路器跳脫之行為,因此調整DC-AC轉換器之輸出功率分配,最後將使用模糊派翠類神經網路取代傳統比例積分控制,以改善響應時間達成更佳的控制效果。
    本文使用Matlab/simulink來模擬微電網中太陽能系統架構以及故障之狀況,驗證本文所提出之控制方法的可行性以及模糊派翠類神經網路之改善效果。實驗方面將使用OPAL-RT即時模擬器與德州儀器公司的DSP TMS320F28335實現硬體迴圈架構以及驗證程式之有效性。
    ;This paper proposes the operation mode and control method of solar energy system in microgrid under normal condition and low voltage fault condition.Normally a solar energy system tracks the peak power output of the solar panel at the maximum power point,and through the DC-AC converter,the power is transmitted to the load or fed back to the grid.During a low voltage fault,the renewable energy device provided by the specification provides a certain proportion of reactive current compensation to assist grid to overcome the short-term voltage drop,and limit the tripping of the circuit breaker during the fault time.Therefore,adjust the output power distribution of the DC-AC converter.Finally,Fuzzy neural Petri net (FNPN) will be used to replace the traditional proportional integral (PI) control to improve the response time and achieve better control effect.
    This paper uses Matlab/simulink to simulate the solar energy system architecture and fault conditions in the microgrid.Verify the feasibility of the control method proposed in this paper and the improvement effect of the Fuzzy neural Petri net.In the experiment, the OPAL-RT real-time simulator and the Texas Instruments DSP TMS320F28335 will be used to implement the hardware loop architecture and verify the effectiveness of the program.
    顯示於類別:[電機工程研究所] 博碩士論文

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