| 摘要: | 近年來，隨著近年半導體、消費性電子產品迅速發展，不論在短距離如晶片間或是長距離光纖通訊，資料傳遞頻寬皆日漸提升。然而，晶片與晶片間資料傳遞的通道頻寬並未隨之上升，使得資料經過傳輸通道的衰減越為嚴重，訊號品質因此下降，造成接收端進行資料判讀的難度大大提升，因此等化器在串列傳輸中扮演重要角色。
本論文提出一資料振幅相關自適應系統，讓等化器可以靈活運用到更寬廣的通道損失應用上，其利用資料振幅電壓位準來判斷資料是否為有效邏輯判斷，電路才會送給自適應系統進行補償調整，使自適應系統能夠正確收斂補償量，以避免資料在經過較高通道損失情況下，資料邏輯判斷錯誤造成自適應機制無法正確收斂的問題發生。而本論文在資料上則是整合連續時間線性等化器以及一階離散決策回授等化器來進行補償消除後游標資料符碼間干擾，以達到降低硬體複雜度與整體功率消耗的效果來補償資料。
本論文使用TSMC 40 nm (TN40G) 1P10M CMOS製程設計，電路操作電壓為0.9 V，輸入資料為20 Gb/s NRZ訊號，並利用PRBS7進行編碼，輸入時脈速率為10 GHz，於佈局後模擬等化器可補償之通道衰減範圍為19-40 dB，在通道衰減19 dB時，補償後之資料的峰對峰值抖動量為16.34 ps，方均根抖動量為4.30 ps;在通道衰減30 dB時，補償後之資料抖動峰對峰值為23.96 ps，方均根抖動量為4.90 ps；在通道衰減40 dB時，補償後之資料抖動峰對峰值為24.60 ps，方均根抖動量為5.34 ps。整體功率消耗為25.78 mW，其中CTLE以及DFE之等化器功率消耗為11.73 mW，自適應機制電路之功率消耗為14.05 mW，微縮後之晶片面積為0.998 mm2，其中核心電路面積為0.033 mm2。
;In recent years, as the rapid development of semiconductors, consumer electronics, artificial intelligence (AI), and internet of things (IoT), the required data rate has been increasing. However, the signal will be serious attenuated since the channel bandwidth is limited. It will make more difficultly to read data at the receiver end (RX). To meet the bandwidth requirement in high speed serial link, the equalizer should be preferentially considered to insert for data compensation. Furthermore, the adaptation would be added in order to allow the equalizer to be used flexibly in different frequency- and length-dependent cable losses application. The adaptive equalizer can adapt to best compensation and restore the signal integrity, so it plays an indispensable role in high speed serial link transmission system.
This thesis proposed a data-amplitude-dependent adaptive system which enables the equalizer to be flexibly applied in wider range of channel loss applications. In adaptive system, it will adjust compensation of equalizer when detecting data voltage level large enough. This method can avoid the problem that the adaptive system can’t converge correctly due to wrong data logic decision in high channel loss. Furthermore, only continuous time linear equalizer (CTLE) and 1-tap discrete-time decision feedback equalizer (1-tap DT-DFE) are be used in data compensation. As the result, the proposed adaptive equalizer system not only reduce the complexity of hardware and power consumption, but also can be widely used for 19-40 dB channel loss application.
This chip is fabricated by TSMC 40 nm (TN40G) 1P10M CMOS process. In simulation result, the input is 20 Gb/s PRBS7 NRZ data, and the 10 GHz half rate clock be adopted. In 19-dB channel loss, the simulated peak-to-peak jitter of equalized NRZ data is 16.34 ps, and the root mean square (RMS) jitter is 4.30 ps. In 30-dB channel loss, the simulated peak-to-peak jitter of equalized NRZ data is 23.96 ps, and the root mean square (RMS) jitter is 4.90 ps. In 40-dB channel loss, the simulated peak-to-peak jitter of equalized NRZ data is 24.60 ps, and the root mean square (RMS) jitter is 5.34 ps. The overall power consumption of whole adaptive equalizer system consumes 25.78 mW at 0.9 V supply voltage, which including power of equalizer 11.73 mW and power of adaptive system 14.05 mW. The chip area with 40 nm which is scaling down by 45 nm is 0.998 mm2 and core area is 0.033 mm2. |
