具資料決策補償技術之16 Gbps半速率時脈與資料回復電路;A 16 Gbps Half-Rate Clock and Data Recovery with Data Decision Compensation Technique

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Title:	具資料決策補償技術之16 Gbps半速率時脈與資料回復電路;A 16 Gbps Half-Rate Clock and Data Recovery with Data Decision Compensation Technique
Authors:	王璽華;Wang, Hsi-Hua
Contributors:	電機工程學系
Keywords:	時脈與資料回復電路;抖動容忍度優化;二進位相位偵測器;Clock and Data Recovery;Jitter Tolerance Enhance;Bang-Bang Phase Detector
Date:	2022-08-11
Issue Date:	2022-10-04 12:07:01 (UTC+8)
Publisher:	國立中央大學
Abstract:	製程隨著莫爾定律發展，晶片中可容納更多電晶體，運算能力大幅提升，因此資料處理及傳輸量倍增。高速串列傳輸已成為傳輸介面的主流並逐漸替代傳統的並列傳輸。例如：PCI-Express、USB、SATA、HDMI、DisplayPort及Ethernet等。傳輸速率不斷倍增下，符碼間干擾產生的影響越來越嚴重以及電路的時間容忍區間也越來越小，惡化誤碼率及抖動容忍度，因此如何維持抖動容忍度及降低誤碼率的發生是必須克服的議題。本論文根據PCIe 4.0規格實現一個具資料決策補償技術之16 Gbps半速率時脈與資料回復電路。決策電路將多階二進位相位偵測器產生的輸出進行運算，得到輸入資料與還原時脈的相位差，透過選擇不同相位的時脈對資料取樣，避免取樣到資料轉態緣，提升抖動容忍度並降低誤碼率；藉由決策電路判斷相位差是否大於0.5 UI，決定交換式二進位相位偵測器的領先落後資訊是否要進行交換，使迴路在相位差大於0.5 UI時仍可往正確方向追鎖。透過此技術不僅可以使相位偵測器可容忍的相位差範圍從0.5 UI 增加至1.0 UI，亦可超過傳統時脈與資料回復電路於高頻抖動容忍度僅能達到0.5 UI的限制。本論文使用TSMC 40 nm (TN40G) 1P10M CMOS製程，操作電壓為0.9 V，輸入資料為PRBS7 16 Gbps，佈局後模擬高頻抖動容忍度與傳統時脈與資料回復電路相比可以改善100 %。量測還原時脈速率為8 GHz，還原時脈之抖動峰對峰值為9.11 pspp，方均根值為1.28 psrms，功率消耗為47.88 mW，晶片面積為0.998 mm2，核心電路面積為0.078 mm2。 ;With the development of Moore′s Law, the semiconductor technology allows more transistors in the chip. The computing power of the chip has been greatly improved, so the processing and transmission of data has increased. High-speed serial link becomes the mainstream of the transmission interface and gradually replaces the traditional parallel communication. For example: PCI-Express, USB, SATA, HDMI, DisplayPort and Ethernet, etc. As the data rate increases, the influence of inter-symbol interference (ISI) becomes serious, and the time tolerance interval of the circuit becomes small. Consequently, bit error rate (BER) and jitter tolerance (JTOL) are degraded. How to maintain jitter tolerance and reduce the bit error rate is an issue that must be overcome. This thesis presents a 16 Gbps half-rate clock and data recovery with data decision compensation technique which takes the PCIe 4.0 specification as a reference material. The proposed decision controller operates the output signal generated by the multi-level bang-bang phase detector (ML BBPD) to obtain the phase error between the data and the recovered clock. Selecting clocks of different phases to sample the data can avoid sampling near the transition edge of the data which improves jitter tolerance and reduces bit error rates. According to whether the phase error is greater than 0.5 UI, the decision controller decides whether the UP and DN signal of the swapping bang-bang phase detector (SBBPD) should be exchanged. Therefore, when the phase error is greater than 0.5 UI, the loop can still be tracked in the correct direction. This technique not only increase the phase error tolerance of the phase detector from 0.5 UI to 1.0 UI, but also exceed the high-frequency jitter tolerance limit of the traditional CDR which is only 0.5 UI. In this thesis, we used TSMC 40 nm (TN40G) 1P10M CMOS process with 0.9 V supply voltage to fabricate the chip and the input data is PRBS7 16 Gbps NRZ signal. In the post-layout simulation, high-frequency jitter tolerance compared to conventional bang-bang CDR is improved by 100 %. At 8 GHz, the measured jitter of the recovered clock is 9.11 pspp and 1.28 psrms, and the power consumption is 47.88 mW. The chip area is 0.998 mm2 and the core area is 0.078 mm2.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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