本論文提出採用穩懋半導體公司(WINTM)之0.25-µm GaN/SiC製程與砷化鎵積體被動元件製程製造C頻段之多悌功率放大器、穩懋半導體公司之0.15-µm InGaAs pHEMT製程製造Ka頻段之F類連續模式功率放大器與台灣積體電路製造公司(tsmcTM)之90 nm互補式金氧半導體製程製造C頻段之I/Q發射機。 第一顆晶片為氮化鎵與砷化鎵被動積體元件製造之C頻段兩級功率放大器，採用多悌負載調變電路架構，藉以提升功率放大器回退時效率，氮化鎵晶片尺寸為1.15 mm2，砷化鎵晶片尺寸為7.03 mm2，量測頻寬為3.6 - 4.5 GHz，最大傳輸增益為18.5 dB，測得飽和輸出功率為38.4 dBm、最大增益附加效率為32.8 % 與回退6 dB時增益附加效率達24.9 %。 第二顆晶片為砷化鎵之Ka頻段兩級功率放大器，輸出匹配網路採用F類連續模式，藉以提升電路整體效率，達到高效率與寬頻之性能，晶片面積為1.08 mm2，量測1 dB頻寬為25 - 30 GHz，最大傳輸增益為17.4 dB，測得飽和輸出功率為 27 dBm、1dB增益壓縮點之輸出功率為26.9 dBm與最大功率附加效率達48.8 %。 第三顆晶片為CMOS之C頻段I/Q發射機，操作於Sub-6GHz 之n79頻段，電路包含I/Q訊號產生器、被動式混頻器、基頻反向放大器與功率放大器，功率放大器使用堆疊式電晶體架構，晶片面積為2.1 mm2，於0 dBm本地震盪功率模擬得輸出功率為23.9 dBm、轉換增益為24.8 dB與整體電路功耗1.06瓦。 ;The thesis developed a C-band Doherty power amplifier(DPA) and a Ka-band Class-F continuous mode technique power amplifier applications in WINTM 0.25-µm GaN/SiC, GaAs integrated passive devices, and 0.15-µm GaAs process. The author also implemented a C-band I/Q (in-phase and quadrature components) transmitter with stacked power amplifier applications in tsmcTM 90-nm CMOS process. The first chip presents a C-band two-stage DPA in GaN and GaAs integrated passive devices (IPD) process. The architecture is Doherty load modulation that improves back-off efficiency of PA. The chip size is 1.15 mm2 of GaN and 7.03 mm2 of GaAs IPD. The measured maximum of small-signal gain is 18.5 dB with the 3-dB bandwidth from 3.6 to 4.5 GHz, the output saturated power is 38.4 dBm, the peak power added efficiency (PAE) is 32.8%, and PAE at back-off 6 dB is 24.9%. The second chip presents a Ka-band two-stage PA in GaAs process. The high efficiency and broadband performances are achieved by using Class-F continuous mode (CM) that is matched for fundamental to third harmonic impedances. The chip size is 1.08 mm2. The measured maximum small-signal gain is 17.4 dB with a 1-dB bandwidth from 25 to 30 GHz, an output saturated power of 27 dBm, an output 1-dB compression point (OP1dB) of 26.9 dBm, and a peak PAE of 48.8%. The third chip implemented a C-band I/Q transmitter in CMOS process. The design includes an I/Q generator, a passive mixer, a baseband inverter, and a power amplifier using stacked transistor architecture. The chip size is 2.1 mm2. With the local oscillator power of 0 dBm, the simulation results show an output power of 23.9 dBm, a conversion gain of 24.8 dB, and a power consumption of 1.06 W.
