運用改良粒子群最佳化演算法之近端串擾消除器電路設計;Design of NEXT Canceller Circuit with Improved Particle Swarm Optimization Algorithm

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Title:	運用改良粒子群最佳化演算法之近端串擾消除器電路設計;Design of NEXT Canceller Circuit with Improved Particle Swarm Optimization Algorithm
Authors:	顏玉家;Yen, Yu-Chia
Contributors:	電機工程學系
Keywords:	近端串擾濾波器;無限脈衝響應濾波器;粒子群最佳化演算法;改良粒子群最佳化演算法;乙太網路;NEXT canceller;IIR filter;Particle swarm optimization;Improved particle swarm optimization;Ethernet
Date:	2022-09-27
Issue Date:	2022-10-04 12:13:01 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文根據IEEE 802.3bz™-2016規範標準[1]，設計近端串擾消除器。近端串擾（Near-end crosstalk, NEXT）在雙絞線中得以抑制，但在不同對雙絞線中存在影響，在高速電路中對訊號品質有較高要求，因此近端串擾需要被解決。一般近端串擾消除器所使用的自適應濾波器為有限脈衝響應濾波器（Finite Impulse response filter, FIR filter），有結構簡單、演算法容易取得的特點，然而隨著近端串擾雜訊通道越長，有限脈衝響應濾波器為與之匹配，階數隨之增加，這使得成本大幅增加，故尋找替代結構成為重要的議題。本論文以無限脈衝響應濾波器（Infinite Impulse response filter, IIR filter）替代有限脈衝響應濾波器，運用其脈衝響應特性，無限脈衝響應濾波器可用較少的階數來模擬通道。自適應無限脈衝響應濾波器採用改良粒子群最佳化演算法，克服誤差平面存在多個局部最小值（Local minimum）問題，使其能收斂至全域最小值（Global minimum），並讓濾波器性能表現符合規範。在硬體實現上，以Verilog 撰寫電路並用NC-Verilog模擬，並透過SMIMS VeriEnterprise Xilinx FPGA驗證電路功能，最終由Design Compiler與IC Compiler以TSMC 40 nm製程來合成電路，並確認運作速度及功能符合規範。;This paper designs a near-end crosstalk canceller according to the IEEE 802.3bz™-2016 specification standard [1]. Near-end crosstalk (NEXT) can be suppressed in twisted pair, but it has influence on different pairs of twisted pair. In high-speed circuits, there is a higher requirement for signal quality, so near-end crosstalk needs to be solved. Generally, the adaptive filter used in the near-end crosstalk canceller is the finite impulse response filter (FIR filter), which has the characteristics of simple structure and easy algorithm. However, as the NEXT noise channel becomes longer, the order of the finite impulse response filter increases in order to match it, which increases the cost significantly. In this paper, the infinite impulse response filter (IIR filter) is used to replace the finite impulse response filter. Using its impulse response properties, infinite impulse response filter can model channels with fewer orders. Adaptive infinite impulse response filter adopts an improved particle swarm optimization algorithm to overcome the problem of multiple local minima in the error plane, so that it can converge to the global minimum value and make the filter performance meet the specifications. In hardware implementation, the circuit is written in Verilog and simulated with NC-Verilog, and the circuit function is verified through SMIMS VeriEnterprise Xilinx FPGA. Finally, Design Compiler and IC Compiler use TSMC 40 nm process to synthesize the circuit, and confirm that the operation speed and function meet the specifications.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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