| 摘要: | 一般常見的氮化鎵電晶體使用一層AlGaN/GaN形成的2DEG 通道進行電晶體的導通，多層通道磊晶的使用也有結構上的限制，為了使多層通道的電晶體達到正的臨界電壓，需要設計奈米等級的鰭寬度(WFin)，使閘極能有效的控制每個通道形成增強型的工作條件。本論文研究內容為探討掘入式(Gate recess)三閘極(Tri-gate)增強型金絕半場效電晶體，搭配AlGaN/GaN/AlGaN/GaN dual channel的磊晶層設計，掘入式結構設計透過蝕刻深度的不同，確認電晶體電性及臨界電壓對蝕刻深度的變化，搭配三閘極結構設計，在閘極位置蝕刻微米等級的數個並列溝槽(Trench)，定義出鰭形(Fin shaped)溝槽，達成提高閘極控制的能力。同時探討在閘極掘入深度從40奈米到50奈米，蝕刻深度變化對臨界電壓之影響。
電晶體製程步驟中，使用氬離子佈植隔絕方式進行元件的製程，元件經由氬離子佈植絕緣之後，會使用ICP-RIE進行溝槽及閘極掘入的蝕刻，閘極掘入的蝕刻深度分別為40、45、50奈米，蝕刻之後會使用稀釋一定比例的BOE、HCl和TMAH溶液對蝕刻表面進行清洗，接著透過ALD沉積20 奈米的氧化鋁(Al2O3)當作閘極絕緣層，最後完成的元件具有2微米的溝槽寬度(WTrench)及2微米的鰭寬度。
元件的最大汲極電流、導通電阻、最大增益轉導值，最小次臨界擺幅，在無閘極掘入的元件比其他閘極掘入深度的元件特性較好。但隨著閘極掘入深度變深，得到臨界電壓增加的變化，當閘極掘入深度來到50奈米時，可得到具有1.46 V的臨界電壓，144.81 mA/mm的汲極電流和4.52 108的電流開關比。藉由電流和電容遲滯量測可估算各閘極掘入深度的元件介面缺陷密度，搭配經稀釋一定比例的BOE、HCl和TMAH溶液進行蝕刻表面處理，得到在界電層與半導體的界面缺陷密度最低約為7.86 1011 eV-1cm-2和0.37 V的遲滯電壓變化量。研究顯示了雙通道對於元件閘極掘入後臨界電壓變化量較小，可從雙通道與單通道元件的模擬結果中同時觀察，雙通道元件在不同閘及掘入後對臨界電壓的變化量較單通道元件的變化量小。
;Generally, traditional GaN transistors use only one 2DEG channel formed AlGaN/GaN layer to conduct drain current. The use of multi-layer channel epitaxy also has structural limitations. In order to make the multi-layer channel transistor reach a positive threshold voltage, it is necessary to design the nanoscale fin width (WFin) for the gate to effectively control each channel. The research content of this paper is to discuss the gate recess tri-gate enhancement mode metal insulator semiconductor field effect transistor, with the epitaxial layer design of the AlGaN/GaN/AlGaN/GaN dual channel. Gate recess structure designed by the difference of etching depth, the change of transistor electrical properties, and threshold voltage to etching depth is confirmed by I-V measurement. With the Tri-gate structure design, several micron-level parallel grooves are etched at the gate position. A fin-shaped trench is designed to improve gate control ability. At the same time, the influence of the etching depth on the threshold voltage is discussed when the gate isolation etching depth is from 40 nm to 50 nm.
In the transistor process step, the device is fabricated by the argon ion implantation isolation method. After the device is isolated by argon ion implantation, ICP-RIE is used for trench and gate recess etching, the etching depth of the gate recess is 40, 45, and 50 nm, respectively. After etching, the etched surface will be cleaned with a certain proportion of BOE, HCl, and TMAH solutions, and then through ALD deposited 20 nm of aluminum oxide (Al2O3) as the gate insulating layer, and the final device had a trench width (WTrench) of 2 μm and a fin width of 2 μm.
The maximum drain current, on-resistance, maximum transconductance value, and the minimum subthreshold swing of the device without gate recess have better characteristics than other devices with gate recess. When the gate recess etching depth becomes deeper, the change of the threshold voltage increases. When the gate recess etching depth reaches 50 nm, a threshold voltage of 1.46 V, a drain current of 144.81 mA/mm, and an on-off current ratio of 4.52 108 V can be obtained. Through current and capacitance hysteresis measurement, the device interface trap density of each gate recess etching depth can be estimated, and the device is dipped in diluted BOE, HCl, and TMAH solutions to reduce the surface damages. The lowest interface trap density is about 7.86 1011 Ev-1cm-2 and a hysteresis voltage of 0.37 V. This study shows that the variation of the threshold voltage of the dual-channel device is smaller, which can be observed simultaneously from the simulation results of the dual-channel and single-channel devices. The variation of the threshold voltage of the dual-channel device is smaller than that of the single-channel device. |
