本論文提出兩個依據Blowfish演算法為架構的資料加密晶片(BECs)。此兩晶片皆可為微處理器的周邊裝置，也可應用於網路相關產品上。使用者可自定64位元的密鑰，對64位元的資料區塊進行加密或解密的運算，其應用範圍可以包括即時資料傳輸及電子資金轉帳方面。 我們利用VHDL'87、Synplify 以及Maxplus II 來設計、合成及模擬BECs，最後使用FPGA (Field Programmable Gate Array) 來實現。 第一種為了面積考量所作的設計，其所需logic cell數量為741，最高工作頻率及資料處理量分別約為42.55 MHz和21.28 Mbit/s。第二種為了速度考量所作的設計，其所需logic cell數量為4698，最高工作頻率及資料處理量則分別約為54.9 MHz和43.92 Mbit/s。 In this thesis, we present two Blowfish encryption chips (BECs) based on the Blowfish algorithm. BECs are microprocessor peripheral devices and might be useful for network devices. They use a 64-bit user-specified key to encrypt and decrypt 64-bit blocks of data. BECs can be used in real time applications and variety of Electronic Funds Transfer applications. To realize the BECs, we use VHDL'87, Synplify, and Maxplus; for designing, synthesizing and simulating. Field Programmable Gate Arrays (FPGAs) are chosen as our target hardware environment. The first design of BEC for area requires 741 logic cells. The maximum operating clock is 42.55 MHz and the corresponding data throughput is about 21.28 Mbit/s. The second design of BEC for speed requires 4698 logic cells. The maximum operating clock is 54.9 MHz and the corresponding data throughput is about 43.92 Mbit/s.
