本論文依據超高速數位用戶迴路 (VDSL) 的標準，針對離散多音調 (DMT) 調變的原理與規格加以討論，並專注於同步迴路中快速富利葉轉換 (FFT) 、符元 (Symbol) 同步、取樣 (Sample) 同步三個模組在數位信號處理器上的實現。經分析比較各種常用的演算法後，採用Radix-2演算法做快速富利葉轉換、運用最大相似 (Maximum likelihood) 原理做符元同步，和利用純數位 (All digital) 方式做取樣同步，最後透過一個可參數化的數位信號處理器 (NCU_DSP) 分析運算複雜度，評估結果發現整個同步迴路須使用約24顆NCU_DSP來實現，且若快速富利葉轉換以全客戶式晶片 (ASIC) 實現，則須使用6顆NCU_DSP。 其中關於內部字元長度 (Internal word length) 問題，本論文亦提出一個有效率解決的方法。它的主要概念是藉由一個和輸入信號相關的補償向量，來省去標準乘法器中非必要的運算。我們將此乘法器命名為低錯誤可縮減位元長度式乘法器，並將其設計成一個可參數化模組，它可以依據設計者給定的位元數，自動產生系統模擬用的C語言碼和硬體設計用的可合成Verilog碼。最後我們成功地將它應用於有線電視傳收器中的波形調整濾波器 (Pulse-shaping filter)，在設計結果和一般計算後刪除方法 (Post truncation) 比較下，發現有50.04%的硬體和33.82%的計算時間被節省下來。 This thesis first discusses the principles and specifications of the DMT technique according to the drafts of the Very high-speed Digital Subscriber Lines (VDSL) standards. We focus on the implementations of the fast Fourier transform (FFT), the symbol synchronization, and the sample synchronization in the synchronization loop using DSP processor approach. After comparing various algorithms, Radix-2 algorithm is used to do the fast Fourier transform, Maximum Likelihood method is used to do the symbol synchronization, and all digital structure is used to do the sample synchronization. The complexity is analyzed with the parameterized digital signal processor (NCU_DSP). The evaluated result concludes that we need about 24 NCU_DSP processors to realize the synchronization loop and 6 NCU_DSP processors if FFT is implemented by ASIC. This thesis also proposes one novel method to solve the errors occurred in the reduced-width multiplier. The main concept of the method is to use an input-number-dependent compensation vector to replace the unnecessary computations in the standard multipliers. The module generator of our proposed method (reduced-width multipliers) is developed. It can automatically generate the C code for the system simulation and the synthesizable Verilog code for the hardware design. The proposal is also successfully applied in pulse-shaping filters of a QAM mode CATV transceiver. The comparison result shows that 50.04% of the hardware area and 33.82% of the critical path delay can be saved while comparing with the post truncation method.
