LPDDR5 基板電路高速訊號完整性分析;High-Speed Signal Integrity Analysis of LPDDR5 Substrate

NCUIR > College of Electrical Engineering & Computer Science > Executive Master of Communication Engineering > Electronic Thesis & Dissertation > Item 987654321/92870

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/92870

Title:	LPDDR5 基板電路高速訊號完整性分析;High-Speed Signal Integrity Analysis of LPDDR5 Substrate
Authors:	陳俊甫;Chen, Chun-Fu
Contributors:	通訊工程學系在職專班
Keywords:	LPDDR;訊號完整性;LPDDR;Signal Integrity
Date:	2023-07-11
Issue Date:	2024-09-19 16:25:02 (UTC+8)
Publisher:	國立中央大學
Abstract:	近年來電子產品講求輕、快、薄，加上AI的崛起，記憶體也需要更快的存取速度，而低功率記憶體進入到第五代的技術，工作頻率也更加的快速，在高頻下，訊號完整性的問題更加的重要。本論文會針對三個部份來進行討訊號完整性討論，第一部分為封裝型型態對於訊號完整性的影響，第二部分為基板結構設計對於訊號完整性的影響，第三部分為Layout設計對於訊號完整性的影響，透過這三部分的研究來找出第五代低功率記憶體的基板設計方向。;In recent years, e lectronic products emphasize lightness, fast, and thinness. With the rise of artificial intelligence, memory also needs to be accessed faster. Low power memory has entered the fifth generation of technology and operates more frequently. At high frequencies , signal integrity becomes more important. This article discusses signal integrity in the following three aspects. The first part examines the effect of package type on signal integrity. The second part focuses on the impact of substrate structure desi gn on signal integrity. Finally, the third part examines the impact of layout design on signal integrity. Through these three studies, we aim to determine the substrate design direction for the fifth generation of low power memory.
Appears in Collections:	[Executive Master of Communication Engineering] Electronic Thesis & Dissertation

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