用於響應穩定性的老化感知平行掃描鏈PUF設計;Aging-aware Parallel Scan-Chain PUF Design for Stability of Responses

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/93149

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/93149

Title:	用於響應穩定性的老化感知平行掃描鏈PUF設計;Aging-aware Parallel Scan-Chain PUF Design for Stability of Responses
Authors:	李宗穎;Tzong-Ying, L
Contributors:	電機工程學系
Keywords:	物理不可仿製功能;平行掃描鍊;老化效應;可測試性設計;Physical unclonable function;Parallel Scan-Chain;Aging Effects;Design for testing
Date:	2022-12-02
Issue Date:	2024-09-19 16:44:34 (UTC+8)
Publisher:	國立中央大學
Abstract:	物理不可仿製功能 Physical Unclonable Function, PUF) 是一種被廣泛研究於硬體安全的技術。透過 PUF 產生器，我們期望獲得不可仿製且無法預測的響應 Responses 並根據不同應用場景作為電路唯一的身分辨識 IDs 或密鑰 Secret Keys 。在硬體上 PUF產生器包含很多種類，例如仲裁器 Arbiter) PUF, 環形震盪器 (Ring-Oscillator) PUF, SRAM PUF, 等等。大部分的 PUF 產生器是需要額外的電路實現且獨立於原始電路。它的額外電路不僅使其容易受到移除攻擊 Removal Attack))，而且還會產生高昂的資源消耗。為了避免上述缺點，有文獻提出了基於延遲 Delay-based 的“平行掃描 PUF Parallel Scan-Chain PUF))”來解決這些問題。它可以通過比較掃描鏈 Scan-Chain 的兩條不同路徑的延遲來實現，這是一種建立在原始電路上的標準 DFT結構。然而這種 PUF 在兩個掃描觸發器之間的不同條件下會受到老化效應的嚴重影響，例如 NBTI、 PBTI 和 HCI。這些將導致原始響應被翻轉並最終導致錯誤，從而造成錯誤更正碼 ( 有較高的複雜性和開銷。在本論文中，我們提出了一種克服老化影響的方法。為了達到預期的目標，我們使用提出的老化補償器 Aging Compensator 來相互抵消老化造成的延遲。實驗結果表明，所提出的老化元件可以防止響應被逆轉並且可以提高可靠度 Reliability 。;Physical Unclonable Function (PUF) has been widely researched as potential security primitive. For applications in the field of hardware security, we expect to obtain the unclonable and unexpected responses that usually served as secret keys or unique IDs in various application scenarios. There are many kinds of PUF for the hardware circuitry, such as Arbiter PUF, Butterfly PUF, Ring-Oscillator PUF, SRAM PUF, Parallel Scan-Chain PUF, and so on. Most existing PUF designs are independent of the original circuit. The extra circuitry for the PUF not only makes it vulnerable to removal attack but also causes high resource overhead. To prevent the above disadvantages, delay-based “Parallel Scan-Chain PUF” is proposed to solve these problems. It is implemented with an arbiter to compare the delay of two different paths of the Scan-Chain, which is a standard DFT structure built on the original circuit. However, this kind of PUF will be severely affected by aging effects, such as NBTI, PBTI, and HCI, due to the conditions of different inputs between two Scan Flip-Flop in normal mode. These will cause the original response to be flipped and eventually lead to errors, resulting in high Error Correction Code (ECC) complexity and overhead. In this thesis, it is proposed a novel method to overcome the effects of aging and enhance reliability. To achieve the desired goal, we analyze the structure of Parallel Scan-Chain PUF and find out the possible causes of error due to aging effects. Next, we use the proposed aging compensator to mutually offset the delay between two different Scan Flip-Flops after aging. Also, we combine the signal gating for the arbiter can not only prevent it from unbalanced aging effects but also save power consumption. Experimental results show that the proposed method can reduce the responses from an average error rate of 39.96% to less than 7.5% within 10 years. Moreover, with the complexity of ECC reduced, it offers ~8x overhead reduction for the BCH encoder and decoder.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	12	View/Open

社群 sharing

Loading...