| 摘要: | 近年來資料傳輸的需求大幅上升，高速串列傳輸介面也陸續推出更高傳輸速率的規格以符合市場需求。傳輸速率逐漸提升的同時，資料經過傳輸通道而受到符碼間干擾越來越嚴重，因而必須使用等化器對資料進行補償以優化接收資料的訊號品質。過去文獻提出各式各樣的等化器架構與電路因應日益增加的傳輸速率，卻因此消耗大量功率或面積，使得串列傳輸系統的能源效率越來越差。與其一味的追求高資料速率的傳輸介面，不如發展能應用在高資料速率上的低功耗技術。
本論文提出一個新架構的等化器，由連續時間線性等化器以及決策回授等化器構成，藉由新的補償方法讓決策回授等化器的時間限制從一個資料位元週期，拓寬為兩個資料位元週期。解放了決策回授等化器的時間限制使得其能使用低功耗電路實現，同時操作於高資料速率。此外，本論文使用自適應系統收斂兩等化器權重，以達到正確的補償量。本論文基於新架構的等化器提出一新的自適應收斂方法，能使用單一自適應機制同時收斂兩等化器的權重。
本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS 製程實現，電路操作電壓為1.0 V，在佈局後模擬的最大輸入資料速率為16 Gbps，輸入時脈頻率為8 GHz，通道衰減為16 dB。核心電路整體功率消耗為5.40 mW，其中連續時間線性等化器為1.78 mW，決策回授等化器為1.12 mW，自適應機制為2.50 mW。量測時最大輸入資料速率為8 Gbps，輸入時脈頻率為4 GHz，通道衰減為21 dB。核心電路整體功率消耗為4.3 mW，其中連續時間線性等化器為1.8 mW，決策回授等化器為0.6 mW，自適應機制為1.9 mW。晶片面積為1.2 mm2，其中核心電路面積為0.047 mm2。
;In recent years, as the demand of data communication has increased rapidly, high speed serial link interface come out with new specification operating at higher data rate to be in line with the market’s demand. While the data rate increases gradually, the channel bandwidth does not follow up. Since then, the data suffers more inter-symbol-interference (ISI), it is necessary to use equalizer compensate the data for ensuring the quality of received signal. The past assay proposed various types of equalizer to deal with the increasing data rate. However, these methods make the energy efficiency of high-speed serial link system worse. Therefore, we should research for low power techniques rather than high data rate interface.
This thesis proposes a new architecture of equalizer, which is composed by continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE). It broadens the time constrain of DFE from one data period to two data period by new compensation method. Since we broaden the time constrain of DFE, we are able to use low power techniques on equalizer. Moreover, this thesis uses adaptive system to converge the weight of both equalizers to obtain correct compensation. This thesis proposes a new adaptive method based on the proposed equalizer, and this allow us to converge boost gain of CTLE and the tap weighting of DFE at the same time with single adaptive system.
The fabricated chip was implemented by TSMC 90 nm (TN90GUTM) 1P9M CMOS process. In post-layout simulation, power supply is 1.0 V, the input data rate is 16 Gbps, the input clock frequency is 8 GHz, and the channel loss is 16 dB. The power consumption of core is 5.40 mW, which includes CTLE consumed 1.78 mW, DFE consumed 1.12 mW, and adaptive system consumed 2.50 mW. In measurement results, the input data rate is 8 Gbps, the input clock frequency is 4 GHz, and the channel loss is 21 dB. The power consumption of core is 4.3 mW, which includes CTLE consumed 1.8 mW, DFE consumed 0.6 mW, and the adaptive system consumed 1.9 mW. The chip area is 1.2 mm2 and the core area is 0.047 mm2. |
