| 摘要: | 隨著電路的操作速度日漸提升，設計一個效能良好的時脈產生器必須考量到輸出抖動、雜訊、功率消耗及面積。使用LC震盪器雖然能有較好的雜訊表現，但需要耗費更多的面積，而使用環形震盪器雖然雜訊表現較差，但面積也相對較小。本論文使用環形震盪器，並配合簡單的相位雜訊與參考突波的抑制技巧，達到低面積與低雜訊之目標。
近年來常見用於降低相位雜訊的電路為次取樣鎖相迴路，其藉由迴路鎖定時移除除頻器的方式，有效地降低相位雜訊。然而次取樣相位偵測器在判斷參考時脈與電壓控制震盪器的高頻輸出訊號之相位差時，對於高頻輸出訊號週期性的干擾造成了電路在頻譜上產生嚴重的參考突波。本論文提出另一種相位偵測的方式，將次取樣鎖相迴路的概念，結合時脈與資料回復電路中的積分式相位偵測器，實現不同頻率之間的相位差偵測，並且能在鎖定時移除迴路中的除頻器以降低相位雜訊，同時對電壓控制震盪器的影響最小化，達到低參考突波、低相位雜訊與小面積的效果。
電路設計與佈局採用TSMC 90 nm 1P9M之CMOS製程實現，電路操作電壓為1 V，輸出頻率為2.4 GHz。使用傳統的電荷幫浦鎖相迴路鎖定時，方均根抖動為2.21 ps，輸出相位雜訊在1 MHz的情況下為-104 dBc/Hz，參考突波與主頻率的能量差為-56.5 dBc。使用積分式相位偵測鎖相電路完成鎖定後，方均根抖動降為1.30 ps，輸出相位雜訊在1 MHz的情況下降至-114 dBc/Hz，參考突波與主頻率的能量差為-54.1 dBc。整體電路的功率消耗為3.77 mW，晶片面積為0.80 mm2，其中核心電路面積為0.027 mm2。
;As circuits operate at higher speeds, designing a clock generator with good performance must account for output jitter, noise, power consumption, and area. Although the LC oscillator has better noise performance, it needs to occupy more area, while the ring oscillator has poor noise performance, but the area is relatively small. In this thesis, a small-area and low-noise phase-locked loop (PLL) is implemented using a ring oscillator combined with a simple technique to suppress phase noise and reference spurs.
In recent years, a common circuit used to reduce phase noise is a sub-sampling phase-locked loop(SSPLL), which effectively reduces phase noise by removing the frequency divider when the loop is locked. However, when the sub-sampling phase detector detects a phase difference between the reference clock and the high-frequency output signal of the voltage-controlled oscillator, periodic disturbances cause serious reference spur problems to the high-frequency output signal. Combining the concept of a sub-sampling PLL with a baud-rate phase detector in a clock and data recovery circuit (CDR), an alternative phase detection method is proposed that can detect the phase difference between two different frequencies. After the loop is locked, the divider in the loop is removed, thus reducing the phase noise. At the same time, the interference caused by the phase detector to the VCO is minimized, and low reference spur, low phase noise and small-area PLL circuits are realized.
This work is fabricated in TSMC 90 nm 1P9M CMOS process, the output frequency is 2.4 GHz when the supply voltage is 1V. The measured phase noise of traditional charge pump PLL(CPPLL) at 1 MHz offset -104 dBc/Hz, the rms jitter is 2.21 ps, and reference spur is -56.5 dBc. The measured phase noise of proposed baud-rate phase detect PLL at 1 MHz offset is reduced to -114 dBc/Hz, the rms jitter is reduced to 1.30 ps, and reference spur is -54.1 dBc. The power consumption of the circuit is 3.77 mW. The die area is 0.080 mm2 and active core area is 0.027 mm2. |
