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    題名: 以OPAL-RT硬體迴圈實現基於深度強化學習演算法與負載預測模型之微電網經濟調度;Implementation of Microgrid Economic Dispatch Based on Deep Reinforcement Learning Algorithms and Load Forecasting Model Using OPAL-RT Hardware in the Loop
    作者: 黃育城;Huang, Yu-Cheng
    貢獻者: 電機工程學系
    關鍵詞: 經濟調度;微電網;負載預測;長短期記憶;深度強化學習;確定性策略梯度;能源管理系統;牛頓粒子群優化;深度Q網路;Economic dispatch;microgrid;load forecasting;long short-term memory;deep reinforcement learning;deep deterministic policy gradient, energy management system;energy management system;Newton-particle swarm optimization;deep Q-network
    日期: 2023-08-03
    上傳時間: 2024-09-19 16:56:49 (UTC+8)
    出版者: 國立中央大學
    摘要: 本論文對於微電網的能源管理最佳化進行了深入的分析和探討,介紹了微電網的結構和調度模型,並提出了一種結合深度確定性策略梯度(Deep Deterministic Policy Gradient, DDPG)與長短期記憶(Long Short-Term Memory, LSTM)負載預測模型的經濟調度方法,旨在實現微電網的最優調度控制。首先,利用LSTM網路來預測微電網的負載信息,以確定發電機輸出與儲能系統的充放電策略;其次,利用DDPG來實現微電網的最佳化經濟調度,為了驗證結果是否符合電力潮流限制,採用位於台灣澎湖群島的七美島微電網模型進行研究,並將所提出的方法與基於經驗的能量管理系統、牛頓結合粒子群體法和深度Q網路(Deep Q Network, DQN)進行比較;最後,通過使用OPAL-RT即時模擬器和浮點數位訊號處理器構建的硬體迴圈(Hardware In the Loop, HIL)系統,充分驗證和展現所提出方法的有效性。;This study presents an in-depth analysis and exploration of energy management optimization in microgrid. It introduces the structure and scheduling model of microgrid and proposes an economic dispatch method that combines Deep Deterministic Policy Gradient (DDPG) and Long Short-Term Memory (LSTM) load forecasting model to achieve optimal dispatch control in microgrid. Firstly, the LSTM network is utilized to predict the load information in microgrid, determining the output of power generator and the charging/discharging control strategy of a battery energy storage system. Secondly, DDPG is employed to optimize the economic dispatch of the microgrid. To verify the results against power flow constraints, a study is conducted using Cimei Island microgrid model located in the Penghu Islands, Taiwan. The proposed method is compared with experience-based energy management systems, Newton-particle swarm optimization, and Deep Q-Network (DQN). Finally, the effectiveness of the proposed method is fully validated and demonstrated through the Hardware In the Loop (HIL) system, which is built using OPAL-RT real-time simulator with floating-point digital signal processor.
    顯示於類別:[電機工程研究所] 博碩士論文

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