在RFSoC平台環境下雷達目標模擬器與脈衝雷達之設計與實現;Design and Implementation of Radar Target Emulator and Pulse Radar in the RFSoC Platform Environment

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題名:	在RFSoC平台環境下雷達目標模擬器與脈衝雷達之設計與實現;Design and Implementation of Radar Target Emulator and Pulse Radar in the RFSoC Platform Environment
作者:	張育群;Chang, Yu-Chun
貢獻者:	通訊工程學系
關鍵詞:	雷達目標模擬器;時變通道;脈衝雷達;匹配濾波器;峰值檢測器;RFSoC;ZCU111;Block RAM;Cordic
日期:	2023-12-22
上傳時間:	2024-03-05 17:41:11 (UTC+8)
出版者:	國立中央大學
摘要:	本論文著重在 RFSoC 平台環境下雷達目標模擬器和脈衝雷達之設計與實現。雷達目標模擬器用於模擬時變通道的效應，包括時變的延遲、都卜勒頻率偏移與訊號的衰減與增益。脈衝雷達是一種常用的雷達系統，使每個脈衝信號在持續時間內保持恆定的信號水平，從而降低信號處理的複雜度，脈衝雷達的目的在於驗證雷達目標模擬器。本論文在兩台 ZCU111 上實現，一台作為脈衝雷達，另一台作為雷達目標模擬器，先在作為雷達的 ZCU111 透過 DAC 產生脈衝雷達訊號並送進雷達目標模擬器的 ADC，依照所設計的時變延遲、相位變化以及訊號衰減來模擬時變通道，雷達目標模擬器的 DAC 會進到雷達的 ADC，最後由雷達收到的訊號做來分析。本篇論文均為八路平行化的硬體架構，包含 Pulse Radar Signal Generator 模組、Matched Filter 模組、Peak Detector 模組、同步接收模組、Delay 模組(Block RAM)、相位旋轉模組(Cordic)、訊號衰減模組以及 RF Data Converter 來實現。;This paper focuses on the design and implementation of Radar Target Emulator and Pulse Radar in the RFSoC Platform Environment. The Radar Target Emulator is employed to simulate the effects of time-varying channels, including time-varying delay, Doppler frequency shift, signal attenuation and gain. Pulse Radar, a commonly used radar system, maintains a constant signal level for each pulse signal within its duration, reducing the complexity of signal processing. The purpose of the Pulse Radar is to validate the Radar Target Emulator. This paper presents the implementation of Radar Target Emulator and Pulse Radar transmitter and receiver system on two ZCU111 boards. One board is used as the Pulse Radar, and the other as the Radar Target Emulator. The radar signal is generated on the ZCU111 board acting as the Pulse Radar and is sent to the Radar Target Emulator’s ADC via radar’s DAC. The Radar Target Emulator then emulates the target signal based on designed time-varying delay, phase variation and signal attenuation. The output from the Radar Target Emulator’s DAC is fed back to the radar’s ADC, and the receiver signal is then analyzed by the radar. The hardware architecture employed in this paper is eight-way parallelized, incorporating modules such as the Pulse Radar Signal Generator module, Matched Filter module, Peak Detector module, Synchronous Receiver module, Delay module (Block RAM), Phase Rotation module (Cordic), Signal Attenuation module, and RF Data Converter.
顯示於類別:	[通訊工程研究所] 博碩士論文

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