隨著製程的日新月異， 使得電晶體不斷的縮小，得到了運算速度提升、消耗功率降低等諸多好處，但同時產生了晶圓良率的下降，在探針測試(Probe testing)階段會對所有晶粒做電性測試，未能通過此檢測的晶粒會被標記為壞晶粒，最後形成整張晶圓圖，我們能透過晶圓圖上壞晶粒所形成的形狀，來找出特定的製程錯誤，過去以人工對晶圓圖瑕疵樣態做識別，雖然能直覺的進行分類，但也耗費了大量時間與人力，為了解決上述的問題，我們希望以一套自動化系統去對晶圓圖做瑕疵樣態的識別。本論文可以分為兩個階段，第一階段使用連通分量分析對壞晶粒進行分群處理，再將晶圓圖進行圓形切割，分為內、中、外三個區域計算其特徵參數，我們針對每一個晶圓圖的特徵參數選擇合適的群聚濾波器，濾除掉對顯著樣態沒有太大影響的離群晶粒，第二階段則利用深度學習中的卷積神經網路將晶圓圖分為九種瑕疵樣態，我們的方法運算時間為每張晶圓圖17.56毫秒，八種樣態精度可達到96.03%，並給予原先定義無樣態的None一個參考。;Due to the progress of manufacturing process, transistor size has reduced but circuit size has increased nowadays. Defects on a wafer have increased, affecting the yield and increasing the cost. During probe test on all dies of a wafer, dies failing to pass test are marked as bad dies. Defect pattern wafer maps are constructed by these bad dies. We can find out specific process errors by analyzing defect patterns, especially efficient if using an automatic system to analyze wafer maps. In the first stage of this thesis, we preprocess wafer maps by using connected component analysis to group bad dies and calculating the average clustering parameters. We carry out circular segmentation for each wafer map, i.e. dividing the map into inner, middle and outer regions, and analyze their characteristics. We obtain the characteristic parameters such as edge bad die proportion, density of bad dies and BD focus, among which the last one represents the key distribution area of bad dies. We classify wafer maps according to the key distribution of bad dies and formulate a filter selection strategy to filter out suitable outliers to obtain required clusters. In the second stage we use CNN for the remaining clusters to classify nine defect patterns on the processed wafer maps. The accuracy of our experiment is 85.36% for nine types of defect patterns, and the accuracy of eight types other than None reaches 96.03%. Our method can classify those maps that may not easy to be recognized. The average speed of our method is 17.56 milliseconds per wafer map.
