新穎極小化高密度三維整體堆疊式1T-nF電流熔絲一次性編程記憶體晶片;Novel Ultra Scaled High-Density 3D Stacking Monolithic 1T-nF Electromigration (eFuse) One-Time Programmable Memory

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/93577

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/93577

Title:	新穎極小化高密度三維整體堆疊式1T-nF電流熔絲一次性編程記憶體晶片;Novel Ultra Scaled High-Density 3D Stacking Monolithic 1T-nF Electromigration (eFuse) One-Time Programmable Memory
Authors:	繆旻倫;Miao, Min-Lun
Contributors:	電機工程學系
Keywords:	一次性編程記憶體;高密度;多位元存儲;One-Time Programmable Memory;High-Density;Multi-bit Storage
Date:	2024-01-11
Issue Date:	2024-09-19 17:20:29 (UTC+8)
Publisher:	國立中央大學
Abstract:	由於物聯網蓬勃發展，市場上各種電子產品為了持久的數據和安全碼存儲，使得一次性編程(OTP)記憶體被加以利用，其存儲的數據在編程後無法更改，研究表明過去十年各種產品中所使用的位元數急遽增加，這導致了晶片設計所需給予OTP記憶體陣列的佈局面積增加，其面積設計問題值得深入研究。本次設計使用熔絲崩潰的機制，在編程時通過加壓產生大電流通過匯流流經熔絲處，於熔絲處通過電遷移使其組態產生轉變，使熔絲從低阻值~50 Ω轉為高阻值3K~10G Ω從而實現編程，傳統的熔絲選用Poly-Fuse，隨著製成微縮目前以選用Metal-Fuse為多數，選用金屬層來當作熔絲能夠實現3D集成堆疊於MOSFET上方縮小佈局面積的使用。由於熔絲崩潰主要是取決於電遷移的力量，理論上設計熔絲的截面積越小，所需使用的電壓電流以及編程的所需時間也能夠變小，具有隨著製成微縮的能力。目前已發展的eFuse一次性編程記憶體其記憶胞設計皆僅只使用一根熔絲來形成，通常採取1T-1F，意即一個記憶胞僅儲存了一個位元，本計畫提出了創新的1T-nF的eFuse OTP NVM的架構，通過使用多層金屬層來做為熔絲，在編程時指定目標金屬層來流經大電流，相比於傳統的1T-1F架構，本次研究設計之1T-nF架構在一個記憶胞能夠儲存n個位元，大幅縮小了佈局面積。本研究設計eFuse OTP NVM的Bit Cell面積僅有0.447µm^2，編程電壓僅為1.8V，遠低於反熔絲崩潰所需之編程電壓4~5V，與其所運用周邊電路進行讀取速度15ns，且金屬熔絲經過讀取干擾測試電熔絲重複讀取〖10〗^12次與資料保存可靠度測試於200°C烘烤一個月皆未發現金屬熔絲發生阻態的改變，此設計可有效縮小目前eFuse OTP NVM陣列所占面積過大之問題。 ;Due to the flourishing development of the Internet of Things (IoT), various electronic products in the market are utilizing One-Time Programmable (OTP) memory for persistent data and security code storage. The stored data in OTP memory cannot be altered after programming. Research indicates a significant increase in the number of bits used in various products over the past decade, leading to an increased layout area for OTP memory arrays in chip design, prompting the need for in-depth investigation into area design issues. In this thesis, a mechanism involving the breakdown of fuses is employed. During programming, a high current is generated by applying pressure, flowing through the fuse location. Electromigration at the fuse location induces a configuration change, transforming the fuse from a low resistance value (~50 Ω) to a high resistance value (3K~10 GΩ), achieving the programming functionality. Traditional fuses used Poly-Fuse, but currently, Metal-Fuse is preferred, utilizing a metal layer for 3D integration stacked above MOSFET to reduce layout area. As fuse breakdown primarily depends on the force of electromigration, theoretically, designing a smaller cross-sectional area for the fuse reduces the required voltage, current, and programming time, demonstrating scalability with technology scaling. Existing eFuse single programmable memory cells typically use only one fuse to form a memory cell, usually adopting a 1T-1F configuration, meaning one memory cell stores one bit. This project proposes an innovative 1T-nF eFuse OTP NVM architecture, utilizing different metal layers as fuses. During programming, a target metal layer is specified to carry a high current. Compared to the traditional 1T-1F structure, the 1T-nF architecture in this study allows one memory cell to store n bits, significantly reducing the layout area. The bit cell area of the designed eFuse OTP NVM in this research is only 0.447µm^2, with a programming voltage of 1.8V, much lower than the 4-5V required for anti-fuse breakdown. It achieves a reading speed of 15ns with peripheral circuits and undergoes interference testing, repeated fuse reading of 〖10〗^12 times, and data retention reliability testing at 200°C for a month without observing changes in the metal fuse resistance state. This design effectively addresses the issue of the excessive footprint of current eFuse OTP NVM arrays.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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