具自適應迴路增益控制器之 5 Gbps 相位內插式 時脈與資料回復電路;A 5 Gbps PI-based Clock and Data Recovery with Adaptive Loop Gain Controller

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Title:	具自適應迴路增益控制器之 5 Gbps 相位內插式時脈與資料回復電路;A 5 Gbps PI-based Clock and Data Recovery with Adaptive Loop Gain Controller
Authors:	廖品媗;Liao, Pin-Hsuan
Contributors:	電機工程學系
Keywords:	時脈與資料回復電路;抖動容忍度;Clock and Data Recovery;CDR;Jitter tolerance
Date:	2024-01-22
Issue Date:	2024-09-19 17:21:10 (UTC+8)
Publisher:	國立中央大學
Abstract:	近年來，隨著半導體產業的迅速發展，產品應用需要更高的資料傳輸頻寬，高速串列傳輸技術成為現在資料傳輸的主流。在串列傳輸系統中，接收端需要使用時脈與資料回復電路來重新調整輸入資料的時脈，以確保正確的資料還原。然而，系統中可能存在各種雜訊和訊號衰減，導致誤碼率上升，因此提升抖動容忍度、減少誤碼率成為時脈與資料回復電路中的設計目標。本論文根據 USB 3.2 gen 1 規格實現一個具自適應迴路增益控制器之 5 Gbps 相位內插式時脈與資料回復電路。透過觀察相位旋轉器旋轉狀況，自適應迴路增益控制器偵測輸入資料的抖動頻率資訊，切換資料回復迴路的迴路增益，以達到在不同的抖動頻率下，優化系統的產生的抖動，提升整體電路的抖動容忍度，降低誤碼率。自適應迴路增益改善了 132% 的低頻抖動容忍度和 17% 高頻抖動容忍度。本論文使用用 TSMC 90 nm (TN90GUTM) 1P9M CMOS 製程來實現，電路操作電壓為 1 V，晶片面積為 1.49 mm2，核心電路面積為 0.066 mm2，輸入資料速率為 5 Gbps 時，還原時脈的峰對峰值抖動為 14.7 pspp，方均根值抖動為 3.46 psrms，消耗功率為 31.04 mW。;In recent years, with the rapid development of the semiconductor industry, products require higher data transmission bandwidth, and high-speed serial transmission technology has become the mainstream for data transmission. In serial transmission systems, the RX needs to use clock and data recovery circuits (CDR) to readjust the input data clock to ensure accurate data recovery. However, various noise and signal attenuation may exist in the system, leading to an increase in error rates. Therefore, improving jitter tolerance (JTOL) and reducing Bit-Error-Rate (BER) have become design goals in clock and data recovery circuits. This paper presents the implementation of a 5 Gbps phase-interpolator based clock and data recovery circuit with an adaptive loop gain controller (ALGC) based on the USB 3.2 Gen 1 specification.The adaptive loop gain controller detects the jitter frequency information of the input data, switches the loop gain of the data recovery loop, and optimizes JTOL under different jitter frequencies. This enhances the overall circuit′s jitter tolerance and reduces error rates. The adaptive loop gain improves low-frequency jitter tolerance by 132% and high-frequency jitter tolerance by 17%. The circuit is implemented using the TSMC 90 nm (TN90GUTM) 1P9M CMOS process, operates at 1 V, with a chip area of 1.49 mm², a core circuit area of 0.066 mm². At a data rate of 5 Gbps, the peak-to-peak jitter of the recovered clock is 14.7 pspp, the root mean square jitter is 3.46 psrms, and the power consumption is 31.04 mW.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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