使用傳輸線基準全通網路之 Ka 頻段四位元 CMOS 被動式相位偏移器;A Ka-Band 4-Bit CMOS Passive Phase Shifter Using Transmission-Line-Based Quasi-All-Pass Networks

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题名:	使用傳輸線基準全通網路之 Ka 頻段四位元 CMOS 被動式相位偏移器;A Ka-Band 4-Bit CMOS Passive Phase Shifter Using Transmission-Line-Based Quasi-All-Pass Networks
作者:	翁育愷;Weng, Yu-Kai
贡献者:	電機工程學系
关键词:	相位偏移器;Phase shifter
日期:	2024-01-23
上传时间:	2024-09-19 17:21:36 (UTC+8)
出版者:	國立中央大學
摘要:	在本論文中，我們基於傳輸線基準全通網路架構理論來實現 Ka 頻段的數位被動式相位偏移器。在第二章中，我們採用傳輸線基準全通網路架構，並且使用 TSMC 0.18-µm CMOS 製程，重新設計 Ka 頻段中心頻率為 35 GHz 的 90◦ 相位偏移器。此電路為先前實驗室洪志恩學長的電路 [1] 使用傳輸線基準全通網路之 35 GHz 90◦ 相位偏移器之重新設計，由對比學長量測與模擬結果可以看到，相位偏移量變小且頻偏。我們以先前實驗室學長重新模擬之結果，將此電路傳輸線及電容理論值重新設計，以獲得較佳的頻率響應。模擬結果顯示，相位誤差低於 3◦ 的相對應頻寬可達 26.8 % (33.8 -44.3 GHz)。在頻寬內返回損耗皆大於 19.1 dB，植入損耗皆小於 6.3 dB，振幅誤差皆在 ±0.98 dB 之內。量測結果顯示，相位誤差低於 3◦ 的相對應頻寬可達 30.0 % (36.1-48.7 GHz)。在頻寬內返回損耗皆大於 14.2 dB，植入損耗皆小於 6.1 dB，振幅誤差皆在 ±0.6 dB 之內。由量測結果可得知，我們將學長電路之頻寬由22.5 % 提升至 30.0 %，並使相位偏移量更貼近模擬結果，符合此次重新設計電路之目標。在第三章中，我們採用傳輸線基準全通網路架構，並且使用 TSMC 0.18-µm CMOS 製程，設計 Ka 頻段四位元被動式相位偏移器。此電路為先前實驗室學長洪維鴻的電路 [2] 四位元傳輸線基準全通網路相位偏移器的重新設計。由學長量測結果可以得知，均方根相位誤差大於 19.2◦ 且相位偏移量之頻率響應往高頻頻偏。本次電路設計目標為降低相位誤差及改善高頻之頻偏。此電路中 22.5◦、45◦ 及 90◦ 相移級皆是使用單級傳輸線基全通網路來實現，而 180◦ 相移級是以中心頻率不同的兩級傳輸線基全通網路串接而成，中心頻率分別為 22 GHz 及 51 GHz 並分別稱為 low-band ( LB ) 及 High-band ( HB )。電路中心頻率為 35 GHz，特徵阻抗為 25 Ω ，傳輸線特徵阻抗使用 50 Ω 、電氣長度為 30◦。模擬結果顯示，均方根相位誤差低於 3◦ 的相對應頻寬可達 19.3 % (33.2 -40.3 GHz)。量測結果顯示，在各個狀態下的相移量皆有變小並往高頻頻偏之趨勢，且均方根相位誤差高於 3◦，因此我們重新定義頻寬為均方根相位誤差 10◦ 以內。在頻段內頻寬可達 17 % (36.2 -42.9 GHz)。輸入返回損耗與植入損耗則與學長量測結果相差不多。與學長論文 [2] 之量測結果對比可得知，我們將最小均方根相位誤差由 19.2◦ 降低到 7.5◦，且改善了相位偏移量之頻偏。在第二顆晶片中，我們將電路加上理想元件以此模擬製程變異，並重新設計微調電晶體及電容值使模擬結果貼合量測結果。重新設計之量測結果顯示，180◦ 相位偏移量變小且每級皆往高頻頻偏，而均方根相位誤差高於 3◦，因此我們重新定義頻寬為均方根相位誤差 6◦ 以內，在頻段內頻寬可達 20.5 % (35.0 -43.0 GHz)。本次電路之重新設計，我們將學長電路之最小均方根相位誤差由 19.2◦ 降低到 4◦，並且將電路中心頻由 45 GHz 調整至 38 GHz，由此驗證了電路重新設計上之改善。並在之後的重新模擬中，模擬元件之寄生效應，將重新模擬結果貼近量測結果。 ;In this thesis, we implemented Ka-band digital passive phase shifters based on the theory of transmission line-based all-pass network. Chapter 2 focuses on the redesign of a 90◦ phase shifter at the center frequency of 35 GHz in the Ka-band, utilizing the transmission line-based all-pass network architecture and TSMC 0.18-µm CMOS process. The circuit is a redesign of the transmission line-based all-pass network 35 GHz 90◦ phase shifter previously designed by Senior Hung Chih-En. Comparing Hung′s measurements and simulations indicates a reduction in phase shift and a movement of frequency response offset. Based on the re-simulation results of Senior Hung Chih-En, we redesigned the theoretical values of the transmission line and capacitance of this circuit to obtain a better frequency response. Simulation results indicate the phase error is within 3◦ and the corresponding bandwidth is 26.8 % (33.8 -44.3 GHz) with return losses bigger than 19.1 dB within the bandwidth, insertion loss below 6.3 dB, and amplitude error within ±0.98 dB. Measurement result demonstrates that the phase error is within 3◦ and the bandwidth is 30.0 % (36.1 -48.7 GHz). Return loss within the bandwidth is above 14.2 dB, insertion loss is below 6.1 dB, and amplitude error is within ±0.6 dB. The measurement indicates that We increased the bandwidth of the senior′s circuit from 22.5 % to 30.0 % and made the phase shift o set closer to the simulation results, which aligns with the redesign objectives. Chapter 3 presents the design of a four-bit passive phase shifter in the Ka-band, based on the transmission line-based all-pass network architecture and TSMC 0.18-µm CMOS process. The circuit is a redesign of Senior Hong Wei-Hong′s four-bit transmission line-based all-pass network phase shifter. The senior′s measurement results indicate that the root mean square phase errors exceed 19.2◦, as well as the phase shift decreases and shifts toward higher frequencies, highlighting the circuit′s objective of mitigating phase errors and addressing high-frequency offsets. The 22.5◦, 45◦, and 90◦ phase shift stages employ single-stage transmission line-based all-pass network, while the 180◦ stage is composed of two in-series transmission line-based all-pass networks with different center frequencies (22 GHz and 51 GHz) referred to as low-band (LB) and high-band (HB). The circuit operates at a center frequency of 35 GHz with a characteristic impedance of 25 Ω, using 50 Ω for transmission line characteristic impedance and an electrical length of 30◦. Simulations show a phase error below 3◦ over a corresponding bandwidth of 19.3% (33.2 -40.3 GHz). Measurement shows that the phase shift in various states reduced, trending towards higher frequency. Therefore, the bandwidth is rede ned as phase errors within 10◦, achieving a bandwidth of 17% (36.2 -42.9 GHz) within this criteria. Comparing with the measurement results of the senior′s paper [2], we can see that we have reduced the minimum root mean square phase error from 19.2◦ to 7.5◦ and improved the frequency response offset of phase shift. In the second chip, we added ideal components to the circuit to simulate process variations and redesigned the transistor and capacitor values to make the simulation results fit the measurement results. The measurement results of the redesign show that the 180◦ phase shift decreased and each stage shifts towards higher frequencies; the root mean square phase error is higher than 3◦, so we redefined the bandwidth as the root mean square phase error is within 6◦. The bandwidth within the frequency band can reach 20.5 % (35.0 43.0 GHz). In this circuit′s redesign, we reduced the minimum root mean square phase error of the senior′s circuit from 19.2◦ to 4◦, and adjusted the circuit center frequency from 45 GHz to 38 GHz, thus verifying the improvement of the circuit′s redesign. And the subsequent re-simulation, the simulation results are close to the measurement results. In the subsequent re-simulation, we simulate the parasitic effect of the components that make the simulation results close to the measurement results.
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