本研究旨在開發一個結合機率神經網路(Probabilistic Neural Network, PNN)與RISC-V的機器學習系統晶片(MLSoC)，以發揮硬體加速的優勢並具備微處理器的泛用性，實現高性能和高度客製化的機器學習應用。透過RISC-V自定義指令和中斷時序設計來優化軟硬體間的數據傳輸和處理流程，增進系統的整體運行效率。本研究採用MIAT系統設計方法論，實現高度的模組化設計，提高系統架構的靈活性。此外，為解決嵌入式系統中記憶體和運算資源達到最佳化設計，本研究提出一個可變精度神經網路開發框架，開發者可以依據需求調整精度。 實驗結果表明，所開發的MLSoC能夠在66毫秒內完成一張64x48大小的影像分割，每個像素的處理時間約為21微秒，消耗能量為0.00504mWh，顯示出系統在保持低功耗的同時，亦能提供高效的運算性能。此外，系統在處理不同精度設定下展現出良好的靈活性和準確性。 本研究提出了一個高效能、低功耗且易於擴展的機器學習軟硬體解決方案，MLSoC的設計在工業應用中尤其具有潛力，適合被廣泛應用於需要即時影像處理和物件識別的場景。本研究的成果也提供了一個實用的參考模型，有助於未來在FPGA上實現更多高效的機器學習解決方案，推動更廣泛的醫療和工業應用。 ;This study aims to develop a machine learning system-on-a-chip (MLSoC) that integrates a Probabilistic Neural Network (PNN) with RISC-V, leveraging the advantages of hardware acceleration while maintaining the versatility of a microprocessor to achieve high performance and highly customizable machine learning applications. The system optimizes data transfer and processing workflows between software and hardware through custom instructions and interrupt handling, enhancing overall system efficiency. The study employs the MIAT system design methodology to achieve a highly modular design, improving the flexibility of the system architecture. Additionally, to address the challenges of memory and computational resource limitations in embedded systems, this study proposes a variable precision neural network development framework, allowing developers to adjust precision according to their needs. Experimental results show that the developed MLSoC can complete the segmentation of a 64x48 image in 66 milliseconds, with each pixel processed in approximately 21 microseconds, demonstrating that the system can provide efficient computational performance while maintaining low power consumption. Furthermore, the system exhibits good flexibility and accuracy under different precision settings. This research provides an efficient, low-power, and scalable hardware solution for machine learning. The MLSoC design has significant potential in industrial applications, especially suitable for scenarios requiring real-time image processing and object recognition. The outcomes of this research also offer a practical reference model for other researchers, facilitating the development of more efficient machine learning solutions on FPGA, thereby advancing broader application development.
