| 摘要: | 隨著科技的發展迎來工業4.0 透過演算法監測和控制機械、機器人等實體設備的自動化系統。近年來的工業控制產品，如交流伺服馬達控制器、工業自動化逆變器、再生能源的功率調節器等用，諸如此類的應用都需要防止危險的電壓或電流，因此工業中的電力電子設備廣泛需要隔離器來保護人員和相鄰的電子設備。
本論文實現應用於光耦合隔離系統接收端電路設計，接收端系統架構主要分為兩個部分，包含類比低通濾波器，用來衰減傳輸端三角積分調變器之高頻量化雜訊，內部電路主要為三階巴特沃斯低通濾波器，時脈資料回復電路以產生濾波器輸入時脈與資料訊號，內部電路分別為相位偵測器(Phase Detector)、電荷泵(Charge Pump)、迴路濾波器(Loop Filter)與電壓控制震盪器(Voltage Control Oscillator)。使用Matlab模擬設計發送端三角積分調變器(SDM)產生1Bit數位訊號，透過頻譜分析訊號雜訊失真比為85.74dB作為後續接收端之輸入訊號。濾波器電路架構採切換式電容濾波器得到較高的線性度，實現接收端類比訊號ENOB大於12Bit之訴求。時脈資料回復電路，採樣頻率(20.48 MHz)為目標頻率，對於瑣相迴路應用相對低速，採用Hogge線性相位偵測器。迴路濾波器使用雙路徑充電泵的濾波器放大電容，減少晶片面積。電壓控制震盪器採用五級電流汲取式反相器產生延遲且震盪。
本電路採用台積電0.18μm CMOS 1P6M製程，晶片面積約佔1.0542×0.969695 mm2，電源供應電壓為1.8V，整體電路功耗為6.01 mW，電路頻寬為40k Hz，超取樣率(OSR)為256，採樣頻率為20.48 MHz，訊號雜訊比(SNR)為79.97dB，總諧波失真(THD)為-83.56dB，訊號對雜訊失真比為78.4dB，ENOB為12.92Bit。;With the advancement of technology ushering in Industry 4.0, automation systems for monitoring and controlling physical equipment such as machinery and robots are facilitated through algorithms. In recent years, industrial control products such as AC servo motor controllers, industrial automation inverters, and power regulators for renewable energy require isolation devices to prevent hazardous voltage or current, thereby ensuring the safety of personnel and adjacent electronic equipment in industrial settings.
The paper implements the design of the receiver circuit applied to the optically coupled isolation system. The receiver system architecture is mainly divided into two parts, including an analog low-pass filter used to attenuate the high-frequency quantization noise of the transmission-side delta-sigma modulator. The internal circuit mainly consists of a third-order Butterworth low-pass filter, a clock data recovery circuit to generate the filter input clock and data signals. The internal circuits include a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator. Matlab simulation is used to design the transmission-side delta-sigma modulator (SDM) to generate 1-bit digital signals, and the signal-to-noise distortion ratio is 85.74dB as the input signal for the subsequent receiver. The filter circuit architecture adopts a switched-capacitor filter to achieve higher linearity, realizing the demand for the analog signal ENOB of greater than 12 bits in the receiver. For the clock data recovery circuit, the sampling frequency (20.48 MHz) is the target frequency, and a relatively low-speed Hogge linear phase detector is used for the jittery loop application. The loop filter uses a filter with amplified capacitors for a dual-path charge pump to reduce chip area. The voltage-controlled oscillator uses a five-stage current-steering inverter to generate delayed and oscillating signals.
The circuit adopts TSMC 0.18μm CMOS 1P6M process, with a chip area of approximately 1.0542×0.969695 mm2. The power supply voltage is 1.8V, and the overall circuit power consumption is 6.01 mW. The circuit bandwidth is 40 kHz, oversampling ratio (OSR) is 256,sampling frequency is 20.48 MHz. The signal-to-noise ratio (SNR) is 79.97 dB, total harmonic distortion (THD) is -83.56 dB, signal-to-noise and distortion ratio (SNDR) is 78.4 dB, and effective number of bits (ENOB) is 12.92 bits. |
