| 摘要: | 在現代的SOC (System On Chip)中，晶片內電網(PDN)扮演著重要的角色。晶片內電網的主要功能是有效分配電源給晶片上的每個元件，確保每個元件都能獲得充足穩定的電源供應。壓降反應(IR-drop)指的是由於晶片內電網的物理結構本身的電阻特性，所造成的從電源端(Current Source)到組件端(Current Sink)的電壓降現象，設計不夠完善的內電網容易導致過大的壓降反應，而過大的壓降反應往往伴隨電路的Timing Violation和Functional Failure…等可靠度方面的問題，這使得壓降反應現象成為IC design中不可忽視的問題。
晶片內電網的規劃通常處於Placement之前的Floorplan階段，因此，在沒有Placement、CTS、以及Routing資訊的前提之下，很難在Physical Design Flow的早期階段就設計出完美的晶片內電網，因此壓降反應是整個Physical Design Flow中經常會遇到的問題。在先前許多關於改善壓降反應的研究中，常見的做法是調整晶片內電網本身的物理結構，具體的實現方法可以是全局地或局部地提高PDN中Power stripes的寬度或密度，這種手法可以有效降低從電源端到組件端的等效電阻，進而降低這兩點之間的壓降反應。
但是隨著擺放與繞線(P&R)的階段往前推進，可用的繞線空間跟著減少，在有限的空間下調整晶片內電網的物理結構很有可能會影響到既有的Placement與Routing結果，換句話說，採用上述這種方法會需要經過多次Placement與Routing的迭代。對於具有上百萬甚至上千萬個標準單元的工業級的設計，儘管有最先進的EDA工具的輔助，不管是Placement或是Routing仍需要數十小時甚至是數天的時間，萬一壓降反應是在Physical Design Flow的末期階段才被診斷出來的話，回過頭去修改內電網的結構就會付出相當大的時間成本，意味著透過調整內電網的物理結構來降低壓降反應遲早會遇到瓶頸。
因此，本篇論文提出了一套透過強化學習的引導在Post-Routing階段添加額外電源線以改善IR-drop的架構。與大多數先前的研究相比，我們的方法具有以下優勢：（1）通過有效利用剩餘的繞線空間來添加電源線，避免了調整PDN主結構的需求，從而最大限度地保留了現有的P&R結果 （2）與啟發式算法相比，強化學習通過試錯不斷更新策略，提供了更好的找到全局最優解的機會。
;In modern System On Chip (SOC) designs, the Power Delivery Network (PDN) plays a crucial role. Its primary function is to efficiently distribute power to every component on the chip, ensuring that each component receives an ample and stable power supply. IR-drop refers to the voltage drop phenomenon from the power source to the component due to the inherent resistance characteristics of the physical structure of the Power Delivery Network (PDN). Insufficiently designed PDN can lead to excessive IR-Drop, and such excessive IR-drop is often accompanied by reliability issues in the circuit, including timing violation and functional failure. This makes the IR-drop phenomenon an issue in IC design that cannot be ignored.
The planning of the PDN typically occurs in the floorplan stage before placement. Therefore, without placement, CTS, and routing information, it is challenging to design a perfect PDN at the early stage of the physical design flow. Hence, IR-drop is a common issue frequently encountered throughout the entire physical design flow. In many previous studies on improving IR-drop, a common approach is to adjust the physical structure of the PDN itself. This can be achieved by globally or locally increasing the width or density of power stripes. This technique effectively reduces the equivalent resistance from the power source to the component, thereby reducing the IR-Drop between these two points
However, as the P&R (Placement and Routing) stages progress, the available routing space decreases. Adjusting the physical structure of PDN within limited space may potentially impact the existing P&R results. In other words, adopting the aforementioned method would require multiple iterations of P&R. For industrial-scale designs with millions or even tens of millions of standard cells, despite the assistance of state-of-the-art EDA tools, both placement and routing still demand dozens of hours or even days. In the scenario where IR-drop is diagnosed in the late stages of P&R, going back to modify the physical structure of PDN would incur significant time costs, implying that the approach of adjusting the physical structure of the PDN itself to mitigate IR-Drop will inevitably encounter bottlenecks.
Therefore, this work proposes an approach to add extra power wires at the post-routing stage to improve IR-drop, with the help of reinforcement-learning. Compared to most previous works, our approach offers the following advantages: (1) By efficiently utilizing remaining routing spaces to add power wires, it avoids the need to adjust the main structure of the PDN, thus maximizing the preservation of existing P&R results. (2) In contrast to heuristic algorithms, reinforcement learning continuously updates strategies through trial and error, providing a better chance of finding the global optimal solution. |
