本論文使用台灣積體電路製造股份有限公司018-µm CMOS 製程設計應用於 n77-n79 頻段之結合 Cold-FET 線化電路之互補式金氧半導體堆疊式功率放大器以及應用於 n79 頻段之 25%責任週期之 I/Q 發射機之設計。 第一顆提出應用於 n77-n79 頻段之結合 Cold-FET 線性化電路之互補式金氧半導體功率放大器，使用堆疊式架構改善 CMOS 製程電晶體本身低崩潰電壓及高膝部電壓之限制，改善電路整體輸出功率，電路匹配採用對稱式磁耦合共振腔變壓器進行設計，達到寬頻之效果，並且在驅動級放大器前置入 Cold-FET 線性化器電路，透過線性化之啟動，使得電路達到增益擴展的效果，達成拉近輸出 1-dB 增益壓縮點功率與輸出飽和功率之間的距離。其操作頻寬為 2.9 - 5 GHz，最大傳輸增益為 21.8 dB，最大輸出功率為27.24 dBm，1-dB 增益壓縮點輸出功率在開啟線性化器後為 26.72 dBm，最高附加效率為 25.57%，晶片面積為 3.69 mm2(2.7 mm × 1.37 mm) 第二顆晶片提出應用於 n79 頻段之四分之一責任週期之 I/Q 發射機電路，本地震盪端口使用電流模態邏輯除頻器後接上方波緩衝器產生四相位訊號，混頻後訊號透過 I/Q路徑直接結合方式求得上邊帶頻率。量測時固定本地震盪驅動訊號為 6 dBm時，操作頻帶為 3 - 4.3 GHz，量測到最大轉換增益為 8.6 dB，輸出 1-dB增益壓縮點功率為 4.61 dBm，輸出三階截斷點為 8.92 dBm，發射機之最佳載波抑制量為 45.3 dBc，最佳邊帶抑制量為44.6 dBc，晶片面積為 1.59 mm2(1.6 mm × 0.98 mm)。 ;This thesis introduces the design of a complementary metal-oxide-semiconductor (CMOS) stacked power amplifier tailored for the n77-n79 frequency bands, integrating a unified Cold FET linearization circuit. The implementation utilizes Taiwan Semiconductor Manufacturing Company′s (tsmc™) 018-µm CMOS process. Furthermore, it presents a 25% duty cycle I/Q transmitter intended for the n79 frequency band. The first chip demonstrates a CMOS power amplifier for the n77-n79 frequency bands, which employed a stacked architecture to overcome inherent limitations in the CMOS process, such as the low breakdown voltage and high knee voltage of the transistors. This configuration significantly enhances the overall circuit output power. Notably, a symmetrically coupled resonator transformer is incorporated for circuit matching, enabling broadband performance. Integration of a Cold-FET linearization circuit before the driver amplifier facilitates gain expansion, reducing the gap between the output 1-dB gain compression point power and the output saturation power. Operating within the bandwidth of 2.9 - 5 GHz, the chip achieves a maximum gain of 21.8 dB, a maximum output power of 27.24 dBm, a 1-dB gain compression point output power of 26.72 dBm and a peak power added efficiency of 25.57% as post linearizer activation. The chip′s physical footprint measures 3.69 mm² (2.7 mm × 1.37 mm). The second chip focuses on a 25% duty cycle I/Q transmitter circuit tailored for the n79 frequency band. The local oscillator port employs a current-mode logic divider followed by a iii square wave buffer to generate quadrature-phase signals. The mixed signal, achieved through direct combination in the I/Q path, produces the upper sideband frequency. Operating within the range of 3 - 4.3 GHz with an optimal local oscillator drive signal of 6 dBm, this chip achieves a maximum conversion gain of 8.6 dB, a 1-dB gain compression point output power of 4.61 dBm, and a third-order intercept point of 8.92 dBm. Impressively, the transmitter demonstrates excellent carrier suppression of 45.3 dBc and sideband suppression of 44.6 dBc.The chip occupies an area of 1.59 mm² (1.6 mm × 0.98 mm).
