應用於脈動陣列深度神經網路加速器之線上內建自我修復方案;Online Built-In Self-Repair Scheme for Systolic Array-Based Deep Neural Network Accelerators

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題名:	應用於脈動陣列深度神經網路加速器之線上內建自我修復方案;Online Built-In Self-Repair Scheme for Systolic Array-Based Deep Neural Network Accelerators
作者:	羅啓翔;Lo, Chi-Hsiang
貢獻者:	電機工程學系
關鍵詞:	深度神經網路;硬體加速器;自我修復;Deep Neural Network;Hardware Accelerator;Built-In Self Repair
日期:	2024-07-29
上傳時間:	2024-10-09 17:15:44 (UTC+8)
出版者:	國立中央大學
摘要:	深度神經網路(DNN)已被廣泛應用於人工智慧的應用。基於脈動陣列的加速器可用於加速DNN的運算。此外，加速器通常會使用較先進的技術節點，這會使得電晶體的可靠度降低。然而，如果加速器適用於安全攸關系統，就必須要具備高可靠度。儘管DNN本身具有抗故障能力，但在設計DNN加速器時採用的計算量減少技術有可能會大大降低其抗故障能力。在本論文中，我們提出獨立權重和與輸入特徵核對和(IWIC)技術，為基於權重固定的DNN硬體加速器提出了一種基於演算法的錯誤偵測方案。與使用過濾器核對和與輸入特徵核對和的卷積進行錯誤偵測的現有方法不同，IWIC技術分別使用權重和與輸入特徵核對和來偵測錯誤，從而降低了面積成本。與現有方法相比，對於資料精度為16位的64x64陣列，所提出的IWIC技術可將硬體開銷減少約25%。特別是，當偵測到錯誤時，IWIC技術可以辨別出有問題的列。我們還在IWIC技術的基礎上，為基於脈動陣列的加速器提出了週期性內置自我修復(PBISR)方案。提出了一故障定位方法給帶有備用行或備用列的PE陣列，以確定故障PE的位置。對於資料精度16位的64x64陣列，故障定位的硬體額外開銷約為2.88%和1.57%。我們還在Xilinx ZCU-102 FPGA平台上實現一8x8 PE陣列，並運行LeNet-5模型來演示IWIC技術。實驗結果顯示，IWIC技術只產生約1.6%的端對端延遲消耗。;Deep neural networks (DNNs) have been widely used for the artificial intelligence applications. Systolic array-based accelerator can be employed for acceleration of DNN computing. Additionally, the accelerator is typically realized with advanced technology nodes which causes the reliability of transistors is decreased. However, if the accelerator is utilized in safety-critical applications, a high reliability feature is necessary. Although DNN possess inherent fault-resilience capability, the computation-reduction techniques employed in the design of DNN accelerators might significantly degrade the fault-resilience capability. In this thesis, we propose an algorithm-based error detection scheme for systolic array-based DNN accelerator with weight stationary data flow using individual weight-sum and input feature map checksum (IWIC) technique. Different to existing works using the convolution of filter checksum and input feature map checksum for the error detection, the IWIC technique executes weight-sum and input feature map checksum individually to reduce the area cost. In comparison with the existing work, the proposed IWIC technique can achieve about 25\% reduction of hardware overhead for a 64x64 systolic array with 16-bit data precision. In particular, the IWIC technique can identify the faulty column when an error is detected. We also propose a periodic built-in self-repair (PBISR) scheme for the systolic array-based accelerator with the IWIC technique. Fault location approaches for the PE array with a spare row or a spare column are proposed to locate the faulty PE. The hardware overhead of the fault location approaches is about 2.88\% and 1.57\% for a 64x64 array with 16-bit data precision, respectively. We also implement an 8x8 PE array with the IWIC technique in the Xilinx ZCU-102 FPGA platform and a LeNet-5 model is run to demonstrate the IWIC technique. Experimental results show that the IWIC technique only incurs about 1.6\% end-to-end latency overhead.
顯示於類別:	[電機工程研究所] 博碩士論文

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