基於動態隨機存取記憶體之近端與內存運算記憶體測試;Testing of DRAMs for Near and In-Memory Computing

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Title:	基於動態隨機存取記憶體之近端與內存運算記憶體測試;Testing of DRAMs for Near and In-Memory Computing
Authors:	張晉維;Zhang, Jin-Wei
Contributors:	電機工程學系
Keywords:	記憶體內運算;記憶體測試;三維隨機存取記憶體;內建自我修復;Computing-In-Memories;Memory Testing;3D DRAM;BISR
Date:	2024-08-21
Issue Date:	2024-10-09 17:21:02 (UTC+8)
Publisher:	國立中央大學
Abstract:	現代馮·諾依曼計算架構在處理數據密集型運算時，數據移動成為性能和功率消耗的瓶頸。內存運算（Computing-in-Memory, CIM）或近端運算（Computing-near-Memory, CNM）被視為具有發展潛力的方法，其中包括在內存陣列或週邊電路中進行運算，或使用3D堆疊架構將內存堆疊於邏輯芯片之上。然而，這些方法增加了架構的複雜性，因此有必要發展有效的測試與修復方法。在本論文中，我們首先對基於DRAM的CIM進行了故障分析，並提出了一種行軍式測試（March Test），以涵蓋內存模式與運算模式下所定義的故障。針對包含N個字元的DRAM CIM，該行軍式測試需要執行12N次寫入操作、5N次讀取操作及6N次運算操作。其次，我們探討了3D DRAM的I/O介面測試與修復。針對具有可重構I/O介面的3D DRAM，我們採用了環回測試方法來檢測可重構I/O介面的參數故障，並提出了一種良好配置識別演算法，用於識別可重構I/O介面的最佳配置。與窮舉搜尋法相比，我們的方法在不犧牲修復率的情況下，對於具有16個通道且每個通道具有128位I/O的4層堆疊3D DRAM，能夠減少22%的測試時間。對於相同I/O條件下的8層堆疊，我們的方法能夠減少26%的測試時間，修復率僅降低0.67%。此外，我們設計了一個基於台積電90nm製程的內建自我修復（Built-In Self-Repair, BISR）電路，用於檢測與修復參數故障。當內存大小為512Mb時，BISR電路的面積開銷僅為0.34%。;Data movement of modern von Neumann computing architecture for data-intensive computation is the bottleneck of performance and energy. Computing-in-memory (CIM) or computing-near-memory (CNM) has been considered as a promising approach, involving computations within memory arrays or peripherals, or using 3D stacking architectures to stack memory on top of logic chips. However, these approaches increase the complexity of the architecture, necessitating the development of effective test and repair methods. In this thesis, we first execute the fault analysis for a DRAM-based CIM and then a March test is proposed to cover the defined faults in both memory mode and computing mode. The March test requires 12N Write operations, 5N Read operations, and 6N Computing operations for a DRAM-based CIM with N words. Secondly, the testing and repair of the I/O interface of 3D DRAMs is introduced. Consider a 3D DRAM with a reconfigurable I/O interface and a loopback test method is used to detect parametric faults of the reconfigurable I/O interface. We propose a good configuration identification algorithm to identify a good configuration of the reconfigurable I/O interface. In comparison with an exhaustive search approach, our approach can reduce 22% of test time without sacrificing the repair rate for a 4-die stacked 3D DRAM with 16 channels, each of which has 128-bit I/Os. For an 8-die stack in the same I/O condition, our approach can reduce test time by 26% at a 0.67% decrease in the repair rate. Additionally, we design a built-in self-repair (BISR) circuit for detecting and repairing parametric faults using the TSMC 90nm standard cell library. The area overhead of the BISR circuit is only 0.34% while the memory size is 512Mb.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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