BiCMOS矽鍺異質接面雙載子功率電晶體設計與高頻基板雜訊隔離之研究; Study on SiGe Power HBT Design and High-Frequency Substrate Noise Isolation in BiCMOS Technology

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題名:	BiCMOS矽鍺異質接面雙載子功率電晶體設計與高頻基板雜訊隔離之研究;Study on SiGe Power HBT Design and High-Frequency Substrate Noise Isolation in BiCMOS Technology
作者:	葉秉君;Ping-Chun Yeh
貢獻者:	電機工程研究所
關鍵詞:	高頻基板雜訊隔離之研究;矽鍺異質接面雙載子功率電晶體設計;BiCMOS;SiGe Power HBT;High-Frequency Substrate Noise Isolation
日期:	2008-07-07
上傳時間:	2009-09-22 11:56:57 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	射頻以及微波電路應用領域中，矽鍺異質接面雙載子電晶體(SiGe HBT)技術已成為具有競爭性的新技術，矽鍺異質接面電晶體技術主要的優點包括、優越的微波功率特性、製造便宜、高的熱傳導係數、可與互補式金屬氧化半導體(CMOS)結合成為整合度高的積體電路。近年來將矽鍺異質接面電晶體應用於未來無線通訊功率放大器也成為相當重要的解決方案與研究方向。此外對高整合度的無線通訊功率放大器產品而言，異質接面功率電晶體有兩個重要的規格:輸出功率(Pout)和功率附加效率(PAE)。其它功率電晶體特性如:增益(gain)、功率密度(power density)與熱穩定度(thermal stability)都應該達到規格與可靠度的要求。然而當異質接面雙載子電晶體操作在高的功率密度，元件的特性將會被電性上的安全操作範圍以及本身所產生的熱效應所限制住。對多射極異質接面雙載子電晶體(multi-finger HBT)而言，元件的接面溫度(junction temperature)上升除了會造成本身的功率損耗之外，還會經由熱耦合(thermal coupling)將熱傳導到鄰近的射極(emitter finger)。當某一特定的射極溫度上升時，將會吸引大部分的電流通過此特定射極，當溫度進一步上升此射極將會成為一個熱區(hot spot)，其它射極將導通越來越少的電流，最後此多射極異質接面雙載子電晶體將產生電流崩潰造成元件的熱不穩定特性產生。此外，射頻系統單晶片(System-on-Chip: SoC)需要將射頻，類比及數位電路整合在相同的晶片上面，由數位邏輯電路所造成的不想要的切換雜訊會對許多高敏感度的高頻類比電路元件如低雜訊放大器(LNA)，壓控振盪器(VCO)產生雜訊擾動互相干擾。因此矽基板的雜訊耦合效應模型應用於射頻系統單晶片(SoC)上也受到相當大的重視與討論。在第二章中，研究集極佈局設計對矽鍺異質接面雙載子功率電晶體電性與電熱特性行為的影響。提出了一個等效電路模型用來研究分析具有不同射極數目的功率電晶體電性與電熱特性行為，經由可靠度驗證結果顯示使用傳統的集極佈局元件(HBT-1)經由十秒的測試，元件就失效故障，主要原因是由於元件本身電熱效應所造成。在相同的測試條件下，使用最佳化的集極佈局元件(HBT-3, type III)可以超過一千秒。元件的大訊號功率特性量測是利用ATN負載-推拉系統操作條件為Class-AB頻率為5.8 GHz。因為HBT-3具有較低的集級電阻與在每個射極的電位差較均勻一致，可以避免元件的熱不穩定進一步造成電熱效應產生，因此HBT-3功率電晶體的功率特性優化指標(figure of merit: FOM) 比HBT-1高出179%。在第三章中，研究不同射極距離(S)佈局設計對矽鍺異質接面雙載子功率電晶體功率特性的影響。利用第二章最佳化的集極佈局元件(type III)結構，研製兩顆具有相同射極面積(8 × 0.6 × 10m2)但不同射極距離的功率電晶體(HBT-1,HBT-2)。HBT-1和HBT-2的射極距離分別為2 m與5m，元件的大訊號功率特性量測同樣是使用ATN負載-推拉系統操作條件為Class-AB頻率為2.4 GHz。因為HBT-2具有較低的元件熱效應，因此HBT-2 功率電晶體的功率特性figure of merit (FOM) 比 HBT-1高出 50%。在第四章中，根據第三章的結果，設計了一個最佳化射極面積為(8 × 0.6 × 10m2)的矽鍺異質接面雙載子電晶體單元晶胞(unit-cell)，利用組合八個功率單元晶胞設計成具有高功率密度與效率的功率電晶體。利用ATN負載-推拉系統操作條件為Class-AB頻率為2.4 GHz量測功率電晶體的大訊號功率特性量測。此功率電晶體的OP1dB達到27.3 dBm，輸出飽和功率為30 dBm換算功率密度為2.6 mW/m2，功率附加效率(PAE)為75%，功率增益為11.4 dB，OP3dB為29.0 dBm。此外此功率電晶體的輸入阻抗高達28歐姆，阻抗轉換比(輸入/系統)為0.56，因此對於必須用高品質係數電感組成的輸入匹配網路的需求將可以變成較有彈性。這個優點可以將此元件較容易的與其他以矽製程做成的高頻收發模組整合成射頻系統單晶片。在第五章中，使用0.35 m SiGe BiCMOS 製程技術設計具有集級開路線性主動偏壓電路的S-Band高效率線性功率放大器。此放大器的輸出級功率電晶體晶胞是由34顆經過電性與熱分析的功率電晶體單位晶胞所組成。和傳統的主動偏壓電路相比較，將集級開路線性主動偏壓電路實施在輸出級功率電晶體晶胞可以改善功率放大器的功率增益、OP1dB、功率附加效率(PAE)與OIP3dB。在第六章中，用S參數量測研究使用0.18 m SiGe BiCMOS製程技術設計的四種矽基板雜訊隔離結構。利用實驗與等效電路模擬分析不同的隔離結構包括由PN接面組成三面的絕緣牆(triple-wall p-n junction isolated walls)，深溝隔絕(deep trench isolation)與雙防護環結構(double P+ guard rings structure)。矽基板雜訊隔離結構B(structure B)可以明顯的降低基板雜訊低於-70 dB，頻率從低頻到20 GHz。矽基板雜訊隔離結C(structure C)可以明顯的降低基板雜訊低於-71 dB頻率到10 GHz 與-56 dB頻率從10 GHz到20 GHz. 建議雜訊隔離結構B(structure B)可應用於一般的射頻系統單晶片設計，雜訊隔離結構C(structure C)可應用於低於10 GHz較敏感的射頻積體電路設計。 Silicon-germanium heterojunction bipolar transistors (SiGe HBTs) technology has emerged as a new contender for RF and microwave applications. The major advantages of SiGe HBT include its superior microwave power performance, low cost, high thermal conductivity, and compatibility for high-level integration with CMOS technology. It has recently attracted a great deal of attention as a promising solution for future wireless power amplifier (PA) applications. Furthermore, two of the most significant HBT power device specifications for highly integrated portable wireless products are the output power (Pout) and the power added efficiency (PAE). Specific characteristics of the power device, such as gain, power density, and thermal stability meet both performance and reliability requirements. However, when operating at a high power density, the ultimate limit on the performance of an HBT is affected by the electrical safe operation area (SOA) and the thermal effects. For a multifinger power device, the increase in junction temperature at any emitter finger not only dissipates the power, but also creates thermal coupling to the other fingers. If the junction temperature of a specified finger increases, it will continue to attract a greater share of the current. The temperature increases further and appears as a hot spot in this finger. In contrast, the remaining fingers draw less current and eventually cause a current collapse. As a result, thermal instability occurs. In addition, RF, analog and digital function blocks need to be integrated with System-on-Chip (SoC) on the same wafer, the substrate coupling model has attracted a lot of attention in SoC desgin. The unwanted switching noise generated by logic circuits causes disturbance and crosstalk to highly sensitive analog components, at high frequencies, such as LNA and VCO. Chapter 1 is the introduction to this paper. Chapter 2 presents the effect of collector layout geometry on the electrical and electro-thermal behaviors in SiGe HBT unit-cell. An equivalent circuit model is proposed to study the electrical and electro-thermal properties on different numbers of emitter fingers. The reliability testing results indicate that HBT-1 using the conventional (type I) layout reached failure mode after being stressed for 10 seconds, which was mainly attributed to the electro-thermal effect. HBT-3 (type III) using the optimized layout survived under the same reliability test for 1000 seconds. The on-wafer power characteristics were measured using ATN load-pull system under CW class-AB operation at 5.8 GHz, the HBT-3 unit-cell yielded an improvement in the power performance figure of merit (FOM) of 179% compared with that of HBT-1, which could be attributed to the fact that HBT-3 had a low collector resistance (RC), and a uniform difference in the △V in each finger, thereby preventing unwanted thermal instability caused by the electro-thermal effect. In chapter 3, the effect of geometry on the RF power performance of SiGe HBT unit-cells is investigated using various emitter finger spacings (S). Two unit-cells, which was designed based on the optimized layout structure (type III) in chapter 2 with the same emitter area of 8 × 0.6 × 10 m2, but with various S values are thoroughly discussed. The S values for the HBT-1 and the HBT-2 unit-cell are 2 m and 5 m, respectively. The on-wafer power characteristics were measured using ATN load-pull system under CW class-AB operations at 2.4 GHz, HBT-2 unit-cell yielded significant improvements in all power performance values compared with HBT-1. An approximately 50% improvement in FOM was achieved, which can be attributed to the fact that HBT-2 has a lower thermal effect than that of HBT-1. In chapter 4, an optimized layout of an eight unit-cells SiGe power HBT with emitter area of 8×0.6×10 m2 based on the results from chapter 3 (type III with S=5m) was designed for high power density and efficiency performance. The on-wafer power characteristics were measured using an ATN load-pull system under CW class-AB operations at 2.4 GHz. The power HBT achieved a 1-dB compression power (P-1dB) of 27.3 dBm and a saturation output power (Psat) of 30 dBm, which was equivalent to a power density of 2.6 mW/m2 for the emitter area. A high peak power added efficiency (PAEmax) of up to 75% was obtained, with a power gain of 11.4 dB at a P3-dB of 29.0 dBm. In addition, the real part of the source impedance (Rin) was measured to be as high as 28 Ω. The impedance transfer ratio, Rin/RSystem was only 0.56, which relaxes the need for a high quality passive component (inductor) for on-chip input matching. This advantage makes it easier for the HBT to be integrated with other silicon-based transceivers in an RF SoC design. In chapter 5, a SiGe HBT unit-cell using 0.35 m BiCMOS technology for an S-Band high efficiency linear power amplifier with an open collector adaptive bias linearizer was designed and fabricated. The electrical and thermal performance of the unit-cell was investigated, and then 34 unit-cells were combined as an output stage power device. An adaptive linearizer for the output stage was constructed using an open collector HBT bias circuit, which improved the Gp, output 1-dB compressed power (OP1dB), power added efficiency (PAE), and output third-order intermodulation point (OIP3) when compared to those of traditional adaptive bias circuits. In Chapter 6, four substrate noise isolation structures using standard 0.18 m SiGe BiCMOS technology were investigated using S-parameter measurements. The experimental and simulated results for different isolation structures, such as triple-wall p-n junction isolated walls, deep trench isolation, and double P+ guard rings structure, are presented. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-wall junction achieved the best isolation at lower frequency range, which \|S21\| was less than - 71 dB from 50 MHz to 10.05 GHz, and - 56 dB from 10.05 GHz to 20.05 GHz. The structure B is good enough and recommends for general purpose RF circuit design whereas structure C can be used in highly sensitive RF circuit block below 10 GHz.
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