在三維的元件模擬中,傳統的分解法產生大量的非零項,它會消耗大量的記憶體空間。然而個人電腦的記憶體空間有其限制而且三維元件的立方體數也將會被限制。因此,在此篇論文中,我們提出了整合型帶狀不完全LU分解法與帶狀LU分解法的模擬器,它可改善記憶體空間不足的問題。我們透過三維的p-n diode來驗證這兩種分解法,並且提出兩種解法器的特性與差異。依據這兩種分解法的特性,我們可選擇合適的解法器來應用在不同的三維元件結構,使得我們的個人電腦能在三維元件特性模擬中發揮最大效能,達成節省記憶體空間的目的。我們也模擬了不同結構的MOSFET,進一步地分析與探討三維MOSFET的特性。 In 3-D device simulation, there will have a lot of nonzero items in matrix solver and cost many memory space. However, the memory space has its limitation and the number of cubic grids will also be confined. In this thesis, we propose the integration matrix solver using Banded incomplete LU method and Banded LU method. The integration solver improves the problem that the memory space is insufficient. We use 3-D p-n device to verify our simulator and find out the feature between the two solvers. Based on the solver property, we select the suitable solver for corresponding 3-D structure. After that, our simulator can save the memory space and make our personal computer working effectively. Finally, we run the simulation of MOSFET in 3-D different structures to analyse the device characteristics.
