DVB-S2 LDPC 高資料率解碼器之FPGA 設計與實現;Design and Implementation of High Throughput DVB-S2 LDPC Decoder with FPGA

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Communication Engineering > Electronic Thesis & Dissertation > Item 987654321/88531

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Title:	DVB-S2 LDPC 高資料率解碼器之FPGA 設計與實現;Design and Implementation of High Throughput DVB-S2 LDPC Decoder with FPGA
Authors:	游理安;You, Li-An
Contributors:	通訊工程學系
Keywords:	低密度奇偶檢查碼;FPGA;ZCU102;第二代數位衛星通訊廣播;軟體定義無線電;解碼器;QC-LDPC;Min-Sum演算法;LDPC code;FPGA;ZCU102;DVB-S2;Soft Defined Radio;Decoder;QC-LDPC Code;Min-Sum Algorithm
Date:	2022-03-10
Issue Date:	2022-07-14 13:52:46 (UTC+8)
Publisher:	國立中央大學
Abstract:	第二代數位衛星通訊廣播(DVB-S2)相較於DVB-S可提供更高的傳輸量，在通道編碼方面除使用LDPC code (Low-Dencity Parity-Check code)以及BCH code (Bose–Chaudhuri–Hocquenghem codes) 提供優異的錯誤更正能力，規格中亦支援多樣化的碼率及碼長以應付各式需求。本論文乃以ZCU102之FPGA硬體架構設計與實現完整DVB-S2中完整的LDPC Code 規格，其中包含各種碼率及碼長的LDPC Code。由於DVB-S2之LDPC校驗矩陣可經過重新排列的方式轉換成Quasi-Cyclic LDPC (QC-LDPC) Code校驗矩陣形式，此本論文之硬體架構包含掃描參數與控制模組、區塊迴旋移動模組、軟式輸入輸出 (soft input soft output, SISO) 解碼計算模組、解碼資訊更新模組。其中碼率與碼長的相關參數是以極特殊的資料結構儲存於記憶體並查表讀取，而SISO解碼演算法則利用Min-Sum演算法來降低硬體複雜度。本論文所實現之解碼器可由外部輸入參數配合控制訊號，使運行中的解碼器能即時切換後續輸入資料對應之LDPC Code 參數進行解碼。 ;Second generation digital video satellite broadcasting(DVB-S2) is a new generation of digital satellite broadcasting standard specified for enhancing transmission capacity of the DVB-S. The main improvement of DVB-S2 relies on the new channel coding scheme which use LDPC(low-dansity-parity-check) code and BCH(Bose–Chaudhuri–Hocquenghem) code. And in the DVB-S2 specification, different code lengths and code rates are also provided, which can correspond to various needs. The research topic of this thesis is on the hardware architecture design and realization of the decoder for the complete DVB-S2 LDPC specification with ZCU102 FPGA evaluation board. Since all the parity matrices specified in the multi-rate DVB-S2 LDPC codes can be transformed in QC(quasi-cyclic)-LDPC codes particular reordering of data and parity-check, we uses a partial parallel and programmable hardware architecture, which is specially designed for QC-LDPC codes and based on a scanning scheme, as the hardware architecture of the decoder. The hardware architrcture includes parallel scanning parameters, control module, block circshift module, and soft input soft output decoding calculation module and decoding information update module. Among them, the related parameters of multi-bit rate and code length are stored in memory and the special data structure is completed in a look-up table mode. The SISO decoding algorithm uses the Min-Sum algorithm as the base to reduce the hardware complexity. The decoder implemented in this thesis can be achieved by external input parameters and control signals to change the corresponding DVB-S2 specification LDPC code rate and code length of the next set of incoming data during operation.
Appears in Collections:	[Graduate Institute of Communication Engineering] Electronic Thesis & Dissertation

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